pc: port 92 reset requires a low->high transition
The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -471,11 +471,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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Port92State *s = opaque;
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int oldval = s->outport;
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DPRINTF("port92: write 0x%02x\n", val);
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s->outport = val;
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qemu_set_irq(*s->a20_out, (val >> 1) & 1);
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if (val & 1) {
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if ((val & 1) && !(oldval & 1)) {
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qemu_system_reset_request();
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}
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}
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