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PPC: use memory API to construct the PCI hole

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Avoid vga.chain4 mapping by constructing a PCI hole for upper
2G of the PCI space.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-09-17 20:30:50 +00:00
parent 3b7653ac48
commit 46f3069cba
4 changed files with 26 additions and 7 deletions
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11
hw/grackle_pci.c
View File

@ -41,6 +41,8 @@
typedef struct GrackleState { typedef struct GrackleState {
SysBusDevice busdev; SysBusDevice busdev;
PCIHostState host_state; PCIHostState host_state;
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
} GrackleState; } GrackleState;
/* Don't know if this matches real hardware, but it agrees with OHW. */ /* Don't know if this matches real hardware, but it agrees with OHW. */
@ -73,11 +75,18 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
qdev_init_nofail(dev); qdev_init_nofail(dev);
s = sysbus_from_qdev(dev); s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(GrackleState, s); d = FROM_SYSBUS(GrackleState, s);
memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
0x80000000ULL, 0x7e000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
&d->pci_hole);
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_grackle_set_irq, pci_grackle_set_irq,
pci_grackle_map_irq, pci_grackle_map_irq,
pic, pic,
address_space_mem, &d->pci_mmio,
address_space_io, address_space_io,
0, 4); 0, 4);

2
hw/ppc_newworld.c
View File

@ -262,8 +262,6 @@ static void ppc_core99_init (ram_addr_t ram_size,
} }
} }
isa_mem_base = 0x80000000;
/* Register 8 MB of ISA IO space */ /* Register 8 MB of ISA IO space */
isa_mmio_init(0xf2000000, 0x00800000); isa_mmio_init(0xf2000000, 0x00800000);

2
hw/ppc_oldworld.c
View File

@ -207,8 +207,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
} }
} }
isa_mem_base = 0x80000000;
/* Register 2 MB of ISA IO space */ /* Register 2 MB of ISA IO space */
isa_mmio_init(0xfe000000, 0x00200000); isa_mmio_init(0xfe000000, 0x00200000);

18
hw/unin_pci.c
View File

@ -41,6 +41,8 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
typedef struct UNINState { typedef struct UNINState {
SysBusDevice busdev; SysBusDevice busdev;
PCIHostState host_state; PCIHostState host_state;
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
} UNINState; } UNINState;
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
@ -215,10 +217,16 @@ PCIBus *pci_pmac_init(qemu_irq *pic,
qdev_init_nofail(dev); qdev_init_nofail(dev);
s = sysbus_from_qdev(dev); s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(UNINState, s); d = FROM_SYSBUS(UNINState, s);
memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
0x80000000ULL, 0x70000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
&d->pci_hole);
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq, pci_unin_set_irq, pci_unin_map_irq,
pic, pic,
address_space_mem, &d->pci_mmio,
address_space_io, address_space_io,
PCI_DEVFN(11, 0), 4); PCI_DEVFN(11, 0), 4);
@ -272,10 +280,16 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
s = sysbus_from_qdev(dev); s = sysbus_from_qdev(dev);
d = FROM_SYSBUS(UNINState, s); d = FROM_SYSBUS(UNINState, s);
memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
0x80000000ULL, 0x70000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
&d->pci_hole);
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq, pci_unin_set_irq, pci_unin_map_irq,
pic, pic,
address_space_mem, &d->pci_mmio,
address_space_io, address_space_io,
PCI_DEVFN(11, 0), 4); PCI_DEVFN(11, 0), 4);