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target/sparc: Move ARRAY* to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 03:26:54 -07:00
parent b88ce6f246
commit 45bfed3b2c
2 changed files with 40 additions and 21 deletions
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4
target/sparc/insns.decode
View File

@ -248,6 +248,10 @@ RETRY 10 00001 111110 00000 0 0000000000000
EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r
EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r
EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r
ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r
ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r
ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}

57
target/sparc/translate.c
View File

@ -722,6 +722,25 @@ static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_ctpop_tl(dst, src2);
}
#ifndef TARGET_SPARC64
static void gen_helper_array8(TCGv dst, TCGv src1, TCGv src2)
{
g_assert_not_reached();
}
#endif
static void gen_op_array16(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_array8(dst, src1, src2);
tcg_gen_shli_tl(dst, dst, 1);
}
static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_array8(dst, src1, src2);
tcg_gen_shli_tl(dst, dst, 2);
}
// 1
static void gen_op_eval_ba(TCGv dst)
{
@ -4211,6 +4230,22 @@ TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1)
TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0)
TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1)
static bool do_rrr(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv, TCGv))
{
TCGv dst = gen_dest_gpr(dc, a->rd);
TCGv src1 = gen_load_gpr(dc, a->rs1);
TCGv src2 = gen_load_gpr(dc, a->rs2);
func(dst, src1, src2);
gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}
TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8)
TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16)
TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32)
static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
{
TCGv dst, src1, src2;
@ -5110,30 +5145,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x009: /* VIS II edge32n */
case 0x00a: /* VIS I edge32lcc */
case 0x00b: /* VIS II edge32ln */
g_assert_not_reached(); /* in decodetree */
case 0x010: /* VIS I array8 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x012: /* VIS I array16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x014: /* VIS I array32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
gen_store_gpr(dc, rd, cpu_dst);
break;
g_assert_not_reached(); /* in decodetree */
case 0x018: /* VIS I alignaddr */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);