pnv/xive2: TIMA support for 8-byte OS context push for PHYP
PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails to check for unpresented pending interrupts for that context. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -596,6 +596,8 @@ static const XiveTmOp xive2_tm_operations[] = {
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NULL },
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{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
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NULL },
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{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx,
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NULL },
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{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
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NULL },
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{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
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@ -597,17 +597,31 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
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void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
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hwaddr offset, uint64_t value, unsigned size)
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{
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uint32_t cam = value;
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uint32_t qw1w2 = cpu_to_be32(cam);
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uint32_t cam;
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uint32_t qw1w2;
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uint64_t qw1dw1;
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uint8_t nvp_blk;
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uint32_t nvp_idx;
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bool vo;
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bool do_restore;
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xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
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/* First update the thead context */
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
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switch (size) {
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case 4:
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cam = value;
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qw1w2 = cpu_to_be32(cam);
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
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break;
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case 8:
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cam = value >> 32;
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qw1dw1 = cpu_to_be64(value);
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memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8);
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break;
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default:
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g_assert_not_reached();
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}
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xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
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/* Check the interrupt pending bits */
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if (vo) {
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