target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -437,6 +437,9 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
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if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
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using_lpae = true;
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} else if (arm_feature(env, ARM_FEATURE_PMSA) &&
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arm_feature(env, ARM_FEATURE_V8)) {
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using_lpae = true;
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} else {
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if (arm_feature(env, ARM_FEATURE_LPAE) &&
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(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
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@ -257,6 +257,10 @@ unsigned int arm_pamax(ARMCPU *cpu);
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static inline bool extended_addresses_enabled(CPUARMState *env)
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{
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uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
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if (arm_feature(env, ARM_FEATURE_PMSA) &&
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arm_feature(env, ARM_FEATURE_V8)) {
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return true;
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}
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return arm_el_is_aa64(env, 1) ||
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(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
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}
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@ -19,6 +19,10 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
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if (el == 2 || arm_el_is_aa64(env, el)) {
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return true;
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}
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if (arm_feature(env, ARM_FEATURE_PMSA) &&
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arm_feature(env, ARM_FEATURE_V8)) {
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return true;
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}
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if (arm_feature(env, ARM_FEATURE_LPAE)
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&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
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return true;
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