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nvme queue

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Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into staging

nvme queue

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# gpg: Signature made Mon 04 Nov 2024 18:11:59 GMT
# gpg:                using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [full]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [full]
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu:
  hw/nvme: remove dead code
  hw/nvme: add NPDAL/NPDGL
  hw/nvme: i/o cmd set independent namespace data structure

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-11-05 14:23:22 +00:00
commit 44a9394b1d
6 changed files with 79 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
hw/nvme/ctrl.c
View File

@ -5692,6 +5692,33 @@ static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req)
return nvme_c2h(n, (uint8_t *)&list, sizeof(list), req);
}
static uint16_t nvme_identify_ns_ind(NvmeCtrl *n, NvmeRequest *req, bool alloc)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid);
trace_pci_nvme_identify_ns_ind(nsid);
if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
return NVME_INVALID_NSID | NVME_DNR;
}
ns = nvme_ns(n, nsid);
if (unlikely(!ns)) {
if (alloc) {
ns = nvme_subsys_ns(n->subsys, nsid);
if (!ns) {
return nvme_rpt_empty_id_struct(n, req);
}
} else {
return nvme_rpt_empty_id_struct(n, req);
}
}
return nvme_c2h(n, (uint8_t *)&ns->id_ns_ind, sizeof(NvmeIdNsInd), req);
}
static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req,
bool active)
{
@ -5946,6 +5973,10 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
return nvme_identify_sec_ctrl_list(n, req);
case NVME_ID_CNS_CS_NS:
return nvme_identify_ns_csi(n, req, true);
case NVME_ID_CNS_CS_IND_NS:
return nvme_identify_ns_ind(n, req, false);
case NVME_ID_CNS_CS_IND_NS_ALLOCATED:
return nvme_identify_ns_ind(n, req, true);
case NVME_ID_CNS_CS_NS_PRESENT:
return nvme_identify_ns_csi(n, req, false);
case NVME_ID_CNS_CTRL:

5
hw/nvme/dif.c
View File

@ -575,11 +575,6 @@ uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req)
uint8_t *mbuf, *end;
int16_t pil = ns->lbaf.ms - nvme_pi_tuple_size(ns);
status = nvme_check_prinfo(ns, prinfo, slba, reftag);
if (status) {
goto err;
}
flags = 0;
ctx->mdata.bounce = g_malloc0(mlen);

11
hw/nvme/ns.c
View File

@ -30,6 +30,7 @@
void nvme_ns_init_format(NvmeNamespace *ns)
{
NvmeIdNs *id_ns = &ns->id_ns;
NvmeIdNsNvm *id_ns_nvm = &ns->id_ns_nvm;
BlockDriverInfo bdi;
int npdg, ret;
int64_t nlbas;
@ -55,6 +56,8 @@ void nvme_ns_init_format(NvmeNamespace *ns)
}
id_ns->npda = id_ns->npdg = npdg - 1;
id_ns_nvm->npdal = npdg;
id_ns_nvm->npdgl = npdg;
}
static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
@ -62,6 +65,7 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
static uint64_t ns_count;
NvmeIdNs *id_ns = &ns->id_ns;
NvmeIdNsNvm *id_ns_nvm = &ns->id_ns_nvm;
NvmeIdNsInd *id_ns_ind = &ns->id_ns_ind;
uint8_t ds;
uint16_t ms;
int i;
@ -72,10 +76,12 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
ns->id_ns.dlfeat = 0x1;
/* support DULBE and I/O optimization fields */
id_ns->nsfeat |= (0x4 | 0x10);
id_ns->nsfeat |= (NVME_ID_NS_NSFEAT_DAE | NVME_ID_NS_NSFEAT_OPTPERF_ALL);
if (ns->params.shared) {
id_ns->nmic |= NVME_NMIC_NS_SHARED;
id_ns->nmic |= NVME_ID_NS_IND_NMIC_SHRNS;
id_ns_ind->nmic = NVME_ID_NS_IND_NMIC_SHRNS;
id_ns_ind->nstat = NVME_ID_NS_IND_NSTAT_NRDY;
}
/* Substitute a missing EUI-64 by an autogenerated one */
@ -770,6 +776,7 @@ static void nvme_ns_realize(DeviceState *dev, Error **errp)
subsys->namespaces[nsid] = ns;
ns->id_ns.endgid = cpu_to_le16(0x1);
ns->id_ns_ind.endgrpid = cpu_to_le16(0x1);
if (ns->params.detached) {
return;

1
hw/nvme/nvme.h
View File

@ -233,6 +233,7 @@ typedef struct NvmeNamespace {
int64_t moff;
NvmeIdNs id_ns;
NvmeIdNsNvm id_ns_nvm;
NvmeIdNsInd id_ns_ind;
NvmeLBAF lbaf;
unsigned int nlbaf;
size_t lbasz;

1
hw/nvme/trace-events
View File

@ -56,6 +56,7 @@ pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctrlid, uint8_t csi) "cid
pci_nvme_identify_ctrl(void) "identify controller"
pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8""
pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32""
pci_nvme_identify_ns_ind(uint32_t nsid) "nsid %"PRIu32""
pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" cntid %"PRIu16""
pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controller capabilities cntlid=%"PRIu16""
pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identify secondary controller list cntlid=%"PRIu16" numcntl=%"PRIu8""

40
include/block/nvme.h
View File

@ -1077,6 +1077,7 @@ enum NvmeIdCns {
NVME_ID_CNS_CS_NS = 0x05,
NVME_ID_CNS_CS_CTRL = 0x06,
NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07,
NVME_ID_CNS_CS_IND_NS = 0x08,
NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
NVME_ID_CNS_NS_PRESENT = 0x11,
NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12,
@ -1087,6 +1088,7 @@ enum NvmeIdCns {
NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a,
NVME_ID_CNS_CS_NS_PRESENT = 0x1b,
NVME_ID_CNS_IO_COMMAND_SET = 0x1c,
NVME_ID_CNS_CS_IND_NS_ALLOCATED = 0x1f,
};
typedef struct QEMU_PACKED NvmeIdCtrl {
@ -1416,9 +1418,28 @@ typedef struct QEMU_PACKED NvmeIdNsNvm {
uint8_t pic;
uint8_t rsvd9[3];
uint32_t elbaf[NVME_MAX_NLBAF];
uint8_t rsvd268[3828];
uint32_t npdgl;
uint32_t nprg;
uint32_t npra;
uint32_t nors;
uint32_t npdal;
uint8_t rsvd288[3808];
} NvmeIdNsNvm;
typedef struct QEMU_PACKED NvmeIdNsInd {
uint8_t nsfeat;
uint8_t nmic;
uint8_t rescap;
uint8_t fpi;
uint32_t anagrpid;
uint8_t nsattr;
uint8_t rsvd9;
uint16_t nvmsetid;
uint16_t endgrpid;
uint8_t nstat;
uint8_t rsvd15[4081];
} NvmeIdNsInd;
typedef struct QEMU_PACKED NvmeIdNsDescr {
uint8_t nidt;
uint8_t nidl;
@ -1439,8 +1460,10 @@ enum NvmeNsIdentifierType {
NVME_NIDT_CSI = 0x04,
};
enum NvmeIdNsNmic {
NVME_NMIC_NS_SHARED = 1 << 0,
enum NvmeIdNsIndependent {
NVME_ID_NS_IND_NMIC_SHRNS = 1 << 0,
NVME_ID_NS_IND_NMIC_DISNS = 1 << 1,
NVME_ID_NS_IND_NSTAT_NRDY = 1 << 0,
};
enum NvmeCsi {
@ -1518,6 +1541,16 @@ enum NvmeIdNsMc {
NVME_ID_NS_MC_SEPARATE = 1 << 1,
};
enum NvmeIdNsNsfeat {
NVME_ID_NS_NSFEAT_THINP = 1 << 0,
NVME_ID_NS_NSFEAT_NSABPNS = 1 << 1,
NVME_ID_NS_NSFEAT_DAE = 1 << 2,
NVME_ID_NS_NSFEAT_UIDREUSE = 1 << 3,
NVME_ID_NS_NSFEAT_OPTPERF_ALL = 3 << 4,
NVME_ID_NS_NSFEAT_MAM = 1 << 6,
NVME_ID_NS_NSFEAT_OPTRPERF = 1 << 7,
};
#define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK)
enum NvmePIFormat {
@ -1873,6 +1906,7 @@ static inline void _nvme_check_size(void)
QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4);
QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16);
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsInd) != 4096);
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096);
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096);
QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);