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target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()

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Support EL2 and EL3 in arm_el_is_aa64() by implementing the
logic for checking the SCR_EL3 and HCR_EL2 register-width bits
as appropriate to determine the register width of lower exception
levels.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Maydell 2016-01-21 14:15:08 +00:00
parent 3355c36053
commit 446c81abf8
1 changed files with 24 additions and 9 deletions
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33
target-arm/cpu.h
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@ -969,18 +969,33 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
/* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.)
/* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
* and if we're not in EL0 then the state of EL0 isn't well defined.)
*/
assert(el == 1 || el == 3);
assert(el >= 1 && el <= 3);
bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower
* exception levels is controlled by the HCR.RW and SCR.RW bits.
/* The highest exception level is always at the maximum supported
* register width, and then lower levels have a register width controlled
* by bits in the SCR or HCR registers.
*/
return arm_feature(env, ARM_FEATURE_AARCH64);
if (el == 3) {
return aa64;
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
}
if (el == 2) {
return aa64;
}
if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
}
return aa64;
}
/* Function for determing whether guest cp register reads and writes should