hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
For SSE-300, the SYSINFO register block has two new registers: * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3; since the SSE-300 can only be configured with a single CPU it is always zero * IIDR is the subsystem implementation identity register; its value is set by the SoC integrator, so we plumb this in from the armsse.c code as we do with SYS_VERSION and SYS_CONFIG Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
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@ -30,6 +30,7 @@ struct ARMSSEInfo {
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int sram_banks;
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int sram_banks;
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int num_cpus;
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int num_cpus;
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uint32_t sys_version;
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uint32_t sys_version;
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uint32_t iidr;
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uint32_t cpuwait_rst;
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uint32_t cpuwait_rst;
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bool has_mhus;
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bool has_mhus;
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bool has_ppus;
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bool has_ppus;
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@ -70,6 +71,7 @@ static const ARMSSEInfo armsse_variants[] = {
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.sram_banks = 1,
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.sram_banks = 1,
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.num_cpus = 1,
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.num_cpus = 1,
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.sys_version = 0x41743,
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.sys_version = 0x41743,
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.iidr = 0,
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.cpuwait_rst = 0,
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.cpuwait_rst = 0,
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.has_mhus = false,
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.has_mhus = false,
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.has_ppus = false,
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.has_ppus = false,
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@ -84,6 +86,7 @@ static const ARMSSEInfo armsse_variants[] = {
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.sram_banks = 4,
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.sram_banks = 4,
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.num_cpus = 2,
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.num_cpus = 2,
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.sys_version = 0x22041743,
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.sys_version = 0x22041743,
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.iidr = 0,
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.cpuwait_rst = 2,
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.cpuwait_rst = 2,
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.has_mhus = true,
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.has_mhus = true,
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.has_ppus = true,
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.has_ppus = true,
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@ -950,6 +953,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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}
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}
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object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
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object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
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info->sse_version, &error_abort);
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info->sse_version, &error_abort);
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object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
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info->iidr, &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) {
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) {
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return;
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return;
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}
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}
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@ -30,6 +30,8 @@
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REG32(SYS_VERSION, 0x0)
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REG32(SYS_VERSION, 0x0)
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REG32(SYS_CONFIG, 0x4)
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REG32(SYS_CONFIG, 0x4)
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REG32(SYS_CONFIG1, 0x8)
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REG32(IIDR, 0xfc8)
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REG32(PID4, 0xfd0)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID6, 0xfd8)
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@ -70,6 +72,24 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset,
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case A_SYS_CONFIG:
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case A_SYS_CONFIG:
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r = s->sys_config;
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r = s->sys_config;
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break;
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break;
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case A_SYS_CONFIG1:
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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return 0;
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break;
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default:
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goto bad_read;
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}
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break;
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case A_IIDR:
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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return s->iidr;
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break;
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default:
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goto bad_read;
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}
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break;
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case A_PID4 ... A_CID3:
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case A_PID4 ... A_CID3:
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switch (s->sse_version) {
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switch (s->sse_version) {
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case ARMSSE_SSE300:
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case ARMSSE_SSE300:
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@ -81,6 +101,7 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset,
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}
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}
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break;
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break;
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default:
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default:
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bad_read:
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SysInfo read: bad offset %x\n", (int)offset);
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"IoTKit SysInfo read: bad offset %x\n", (int)offset);
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r = 0;
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r = 0;
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@ -114,6 +135,7 @@ static Property iotkit_sysinfo_props[] = {
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DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0),
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DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0),
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DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0),
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DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0),
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DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0),
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DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0),
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DEFINE_PROP_UINT32("IIDR", IoTKitSysInfo, iidr, 0),
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DEFINE_PROP_END_OF_LIST()
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DEFINE_PROP_END_OF_LIST()
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};
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};
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@ -39,6 +39,7 @@ struct IoTKitSysInfo {
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uint32_t sys_version;
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uint32_t sys_version;
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uint32_t sys_config;
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uint32_t sys_config;
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uint32_t sse_version;
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uint32_t sse_version;
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uint32_t iidr;
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};
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};
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#endif
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#endif
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