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target-mips: Enable vectored interrupt support for the 74Kf CPU

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Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Maciej W. Rozycki 2014-11-04 15:42:19 +00:00 committed by Leon Alrae
parent 11f5ea105c
commit 4386f08767
1 changed files with 1 additions and 1 deletions
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target-mips/translate_init.c
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@ -334,7 +334,7 @@ static const mips_def_t mips_defs[] =
(1 << CP0C1_CA), (1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
(0 << CP0C3_VInt), (1 << CP0C3_VInt),
.CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4, .CP0_LLAddr_shift = 4,
.SYNCI_Step = 32, .SYNCI_Step = 32,