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vga: sort-of implement word and double-word access modes

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Jazz Jackrabbit has a very unusual VGA setup, where it uses odd/even mode
with 256-color graphics.  Probably, it wants to use fast VRAM-to-VRAM
copies without having to store 4 copies of the sprites as needed in mode
X, one for each mod-4 alignment; odd/even mode simplifies the code a
lot if it's okay to place on a 160-pixels horizontal grid.

At the same time, because it wants to use double buffering (a la "mode X")
it uses byte mode, not word mode as is the case in text modes.  In order
to implement the combination of odd/even mode (plane number comes from
bit 0 of the address) and byte mode (use all bytes of VRAM, whereas word
mode only uses bytes 0, 2, 4,... on each of the four planes), we need
to separate the effect on the plane number from the effect on the address.

Implementing the modes properly is a mess in QEMU, because it would
change the layout of VRAM and break migration.  As an approximation,
shift right when the CPU accesses memory instead of shifting left when
the CRT controller reads it.  A hack is needed in order to write font data
properly (see comment in the code), but it works well enough for the game.

Because doubleword and chain4 modes are now independent, chain4 does not
assert anymore that the address is in range.  Instead it just returns
all ones and discards writes, like other modes.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2014-12-29 14:56:24 +01:00
parent 3f83435042
commit 435262605f
2 changed files with 69 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
hw/display/vga.c
View File

@ -815,25 +815,40 @@ uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
}
if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
/* chain 4 mode : simplest access (but it should use the same
* algorithms as below; see e.g. vga_mem_writeb's plane mask check).
*/
assert(addr < s->vram_size);
return s->vram_ptr[addr];
}
if (s->gr[VGA_GFX_MODE] & 0x10) {
/* chain4 mode */
plane = addr & 3;
addr &= ~3;
} else if (s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) {
/* odd/even mode (aka text mode mapping) */
plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
addr >>= 1;
} else {
/* standard VGA latched access */
plane = s->gr[VGA_GFX_PLANE_READ];
}
if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) {
addr &= ~1;
}
/* Doubleword/word mode. See comment in vga_mem_writeb */
if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) {
addr >>= 2;
} else if ((s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) &&
(s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) {
addr >>= 1;
}
if (addr * sizeof(uint32_t) >= s->vram_size) {
return 0xff;
}
if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
/* chain 4 mode: simplified access (but it should use the same
* algorithms as below, see e.g. vga_mem_writeb's plane mask check).
*/
return s->vram_ptr[(addr << 2) | plane];
}
s->latch = ((uint32_t *)s->vram_ptr)[addr];
if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
/* read mode 0 */
@ -853,8 +868,9 @@ uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
/* called for accesses between 0xa0000 and 0xc0000 */
void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
{
int memory_map_mode, plane, write_mode, b, func_select, mask;
int memory_map_mode, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
int plane = 0;
#ifdef DEBUG_VGA_MEM
printf("vga: [0x" HWADDR_FMT_plx "] = 0x%02x\n", addr, val);
@ -888,9 +904,46 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
/* chain 4 mode : simplest access */
plane = addr & 3;
mask &= (1 << plane);
addr &= ~3;
} else {
if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0) {
mask &= (addr & 1) ? 0x0a : 0x05;
}
if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) {
addr &= ~1;
}
}
/* Doubleword/word mode. These should be honored when displaying,
* not when reading/writing to memory! For example, chain4 modes
* use double-word mode and, on real hardware, would fetch bytes
* 0,1,2,3, 16,17,18,19, 32,33,34,35, etc. Text modes use word
* mode and, on real hardware, would fetch bytes 0,1, 8,9, etc.
*
* QEMU instead shifted addresses on memory accesses because it
* allows more optimizations (e.g. chain4_alias) and simplifies
* the draw_line handlers. Unfortunately, there is one case where
* the difference shows. When fetching font data, accesses are
* always in consecutive bytes, even if the text/attribute pairs
* are done in word mode. Hence, doing a right shift when operating
* on font data is wrong. So check the odd/even mode bits together with
* word mode bit. The odd/even read bit is 0 when reading font data,
* and the odd/even write bit is 1 when writing it.
*/
if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) {
addr >>= 2;
} else if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0 &&
(s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) {
addr >>= 1;
}
if (addr * sizeof(uint32_t) >= s->vram_size) {
return;
}
if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) {
if (mask) {
assert(addr < s->vram_size);
s->vram_ptr[addr] = val;
s->vram_ptr[(addr << 2) | plane] = val;
#ifdef DEBUG_VGA_MEM
printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr);
#endif
@ -900,15 +953,6 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
return;
}
if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0) {
mask &= (addr & 1) ? 0x0a : 0x05;
}
if (s->gr[VGA_GFX_MODE] & 0x10) {
/* odd/even mode (aka text mode mapping) */
addr >>= 1;
}
/* standard VGA latched access */
write_mode = s->gr[VGA_GFX_MODE] & 3;
switch(write_mode) {
@ -973,9 +1017,6 @@ do_write:
/* mask data according to sr[2] */
s->plane_updated |= mask; /* only used to detect font change */
write_mask = mask16[mask];
if (addr * sizeof(uint32_t) >= s->vram_size) {
return;
}
((uint32_t *)s->vram_ptr)[addr] =
(((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
(val & write_mask);

4
hw/display/vga_regs.h
View File

@ -100,7 +100,9 @@
/* VGA CRT controller bit masks */
#define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
#define VGA_CR14_DW 0x40
#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
#define VGA_CR17_WORD_BYTE 0x40
/* VGA attribute controller register indices */
#define VGA_ATC_PALETTE0 0x00
@ -154,6 +156,8 @@
#define VGA_GFX_BIT_MASK 0x08
/* VGA graphics controller bit masks */
#define VGA_GR05_HOST_ODD_EVEN 0x10
#define VGA_GR06_GRAPHICS_MODE 0x01
#define VGA_GR06_CHAIN_ODD_EVEN 0x02
#endif /* HW_VGA_REGS_H */