Includes a headers update against 5.6-current.
- add missing vcpu reset functionality - rstfy some s390 documentation - fixes and enhancements -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEw9DWbcNiT/aowBjO3s9rk8bwL68FAl5XrPASHGNvaHVja0By ZWRoYXQuY29tAAoJEN7Pa5PG8C+vbLwP/jCxQfhEbiGFs3M7Xz6FNXmGQ3Zmw2j2 6YNSK7Qpe9GPYlmU4UyhG83buGX1pTF4YgvmpIlMgm33fGRL7FKVDHCXv8qYRvUF QB/SV/YfoFwVSBtE7uiHLg0/5YtvbK7dwZiWA1bKSOUp4NsZJofL2qqQnP2m9ecA ZRiJxQ2KJjeQ6rLkPHwVkoTut3Xd55HHdKqEo8BVsq1XFKc7nFpE9o4QpuHbODi8 CzGxJSpUImmsk39obY5jYbW8xiVm6xkVbp+bXGBHSOoCOCFeXqE7MjnF7xE7xeVF ST9Jtd/8dFI4v5qVhhfdy/K6EvUoiZ/aUTF1J2PRzg9nueDzYNdJTVVvC/DgCfQn joSVjlvawHKzmVkEWcmj3NxQsT1m9pq77HD3du8miYs48IUmE7qsBmKNp8ToaBSV L99EwujOFXfrqyCPnfycZzVFWG48+ppmF43gKhthKk7EuacdB8NPr6ePuDkZf9DM l6sfjwRGSvZdmgsenvavk12ug433gO2VNxH4AarWNtXq8ADBCtvgQCtEGZMbV+Js dm3uPtVF5RKxoHeuXv7wTgt6TybzPEb0+WSEYEfDyquwKFFAAckFmk6giccusXiA umXvXXmIab/xa2VVRRNUS4Rq4mJ+kXFKpXVgdt633ZwWFc9vQMFowzUo99+1BUfi JX0Bkb4zFbox =zN7w -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200227' into staging Includes a headers update against 5.6-current. - add missing vcpu reset functionality - rstfy some s390 documentation - fixes and enhancements # gpg: Signature made Thu 27 Feb 2020 11:50:08 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [marginal] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [marginal] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [marginal] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20200227: s390x: Rename and use constants for short PSW address and mask docs: rstfy vfio-ap documentation docs: rstfy s390 dasd ipl documentation s390/sclp: improve special wait psw logic s390x: Add missing vcpu reset functions linux-headers: update target/s390x/translate: Fix RNSBG instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
430f63e250
@ -1259,7 +1259,7 @@ S: Supported
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F: hw/s390x/ipl.*
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F: pc-bios/s390-ccw/
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F: pc-bios/s390-ccw.img
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F: docs/devel/s390-dasd-ipl.txt
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F: docs/devel/s390-dasd-ipl.rst
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T: git https://github.com/borntraeger/qemu.git s390-next
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L: qemu-s390x@nongnu.org
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@ -1570,7 +1570,7 @@ F: hw/s390x/ap-bridge.c
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F: include/hw/s390x/ap-device.h
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F: include/hw/s390x/ap-bridge.h
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F: hw/vfio/ap.c
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F: docs/vfio-ap.txt
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F: docs/system/vfio-ap.rst
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L: qemu-s390x@nongnu.org
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vhost
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@ -25,3 +25,4 @@ Contents:
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tcg-plugins
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bitops
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reset
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s390-dasd-ipl
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@ -1,25 +1,28 @@
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*****************************
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***** s390 hardware IPL *****
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*****************************
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Booting from real channel-attached devices on s390x
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===================================================
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s390 hardware IPL
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-----------------
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The s390 hardware IPL process consists of the following steps.
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1. A READ IPL ccw is constructed in memory location 0x0.
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1. A READ IPL ccw is constructed in memory location ``0x0``.
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This ccw, by definition, reads the IPL1 record which is located on the disk
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at cylinder 0 track 0 record 1. Note that the chain flag is on in this ccw
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so when it is complete another ccw will be fetched and executed from memory
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location 0x08.
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location ``0x08``.
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2. Execute the Read IPL ccw at 0x00, thereby reading IPL1 data into 0x00.
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2. Execute the Read IPL ccw at ``0x00``, thereby reading IPL1 data into ``0x00``.
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IPL1 data is 24 bytes in length and consists of the following pieces of
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information: [psw][read ccw][tic ccw]. When the machine executes the Read
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information: ``[psw][read ccw][tic ccw]``. When the machine executes the Read
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IPL ccw it read the 24-bytes of IPL1 to be read into memory starting at
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location 0x0. Then the ccw program at 0x08 which consists of a read
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location ``0x0``. Then the ccw program at ``0x08`` which consists of a read
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ccw and a tic ccw is automatically executed because of the chain flag from
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the original READ IPL ccw. The read ccw will read the IPL2 data into memory
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and the TIC (Transfer In Channel) will transfer control to the channel
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program contained in the IPL2 data. The TIC channel command is the
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equivalent of a branch/jump/goto instruction for channel programs.
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NOTE: The ccws in IPL1 are defined by the architecture to be format 0.
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3. Execute IPL2.
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@ -31,15 +34,18 @@ The s390 hardware IPL process consists of the following steps.
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the real operating system is loaded into memory and we are ready to hand
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control over to the guest operating system. At this point the guest
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operating system is entirely responsible for loading any more data it might
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need to function. NOTE: The IPL2 channel program might read data into memory
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location 0 thereby overwriting the IPL1 psw and channel program. This is ok
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as long as the data placed in location 0 contains a psw whose instruction
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need to function.
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NOTE: The IPL2 channel program might read data into memory
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location ``0x0`` thereby overwriting the IPL1 psw and channel program. This is ok
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as long as the data placed in location ``0x0`` contains a psw whose instruction
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address points to the guest operating system code to execute at the end of
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the IPL/boot process.
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NOTE: The ccws in IPL2 are defined by the architecture to be format 0.
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4. Start executing the guest operating system.
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The psw that was loaded into memory location 0 as part of the ipl process
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The psw that was loaded into memory location ``0x0`` as part of the ipl process
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should contain the needed flags for the operating system we have loaded. The
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psw's instruction address will point to the location in memory where we want
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to start executing the operating system. This psw is loaded (via LPSW
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@ -54,18 +60,17 @@ written immediately after the special "Read IPL" ccw, the IPL1 channel program
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will be executed immediately (the special read ccw has the chaining bit turned
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on). The TIC at the end of the IPL1 channel program will cause the IPL2 channel
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program to be executed automatically. After this sequence completes the "Load"
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procedure then loads the psw from 0x0.
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procedure then loads the psw from ``0x0``.
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**********************************************************
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***** How this all pertains to QEMU (and the kernel) *****
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**********************************************************
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How this all pertains to QEMU (and the kernel)
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----------------------------------------------
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In theory we should merely have to do the following to IPL/boot a guest
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operating system from a DASD device:
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1. Place a "Read IPL" ccw into memory location 0x0 with chaining bit on.
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2. Execute channel program at 0x0.
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3. LPSW 0x0.
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1. Place a "Read IPL" ccw into memory location ``0x0`` with chaining bit on.
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2. Execute channel program at ``0x0``.
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3. LPSW ``0x0``.
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However, our emulation of the machine's channel program logic within the kernel
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is missing one key feature that is required for this process to work:
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@ -89,32 +94,31 @@ Lastly, in some cases (the zipl bootloader for example) the IPL2 program also
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transfers control to another channel program segment immediately after reading
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it from the disk. So we need to be able to handle this case.
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**************************
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***** What QEMU does *****
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**************************
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What QEMU does
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--------------
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Since we are forced to live with prefetch we cannot use the very simple IPL
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procedure we defined in the preceding section. So we compensate by doing the
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following.
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1. Place "Read IPL" ccw into memory location 0x0, but turn off chaining bit.
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2. Execute "Read IPL" at 0x0.
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1. Place "Read IPL" ccw into memory location ``0x0``, but turn off chaining bit.
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2. Execute "Read IPL" at ``0x0``.
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So now IPL1's psw is at 0x0 and IPL1's channel program is at 0x08.
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So now IPL1's psw is at ``0x0`` and IPL1's channel program is at ``0x08``.
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4. Write a custom channel program that will seek to the IPL2 record and then
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3. Write a custom channel program that will seek to the IPL2 record and then
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execute the READ and TIC ccws from IPL1. Normally the seek is not required
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because after reading the IPL1 record the disk is automatically positioned
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to read the very next record which will be IPL2. But since we are not reading
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both IPL1 and IPL2 as part of the same channel program we must manually set
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the position.
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5. Grab the target address of the TIC instruction from the IPL1 channel program.
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4. Grab the target address of the TIC instruction from the IPL1 channel program.
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This address is where the IPL2 channel program starts.
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Now IPL2 is loaded into memory somewhere, and we know the address.
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6. Execute the IPL2 channel program at the address obtained in step #5.
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5. Execute the IPL2 channel program at the address obtained in step #4.
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Because this channel program can be dynamic, we must use a special algorithm
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that detects a READ immediately followed by a TIC and breaks the ccw chain
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@ -126,8 +130,9 @@ following.
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channel program from executing properly.
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Now the operating system code is loaded somewhere in guest memory and the psw
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in memory location 0x0 will point to entry code for the guest operating
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in memory location ``0x0`` will point to entry code for the guest operating
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system.
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7. LPSW 0x0.
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6. LPSW ``0x0``
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LPSW transfers control to the guest operating system and we're done.
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@ -15,3 +15,4 @@ Contents:
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:maxdepth: 2
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qemu-block-drivers
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vfio-ap
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File diff suppressed because it is too large
Load Diff
@ -179,7 +179,7 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
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/* if not Linux load the address of the (short) IPL PSW */
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ipl_psw = rom_ptr(4, 4);
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if (ipl_psw) {
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pentry = be32_to_cpu(*ipl_psw) & 0x7fffffffUL;
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pentry = be32_to_cpu(*ipl_psw) & PSW_MASK_SHORT_ADDR;
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} else {
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error_setg(&err, "Could not get IPL PSW");
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goto error;
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@ -409,6 +409,30 @@ extern "C" {
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#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
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#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
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/*
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* Intel color control surfaces (CCS) for Gen-12 render compression.
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*
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* The main surface is Y-tiled and at plane index 0, the CCS is linear and
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* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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* main surface. In other words, 4 bits in CCS map to a main surface cache
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* line pair. The main surface pitch is required to be a multiple of four
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* Y-tile widths.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
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/*
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* Intel color control surfaces (CCS) for Gen-12 media compression
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*
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* The main surface is Y-tiled and at plane index 0, the CCS is linear and
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* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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* main surface. In other words, 4 bits in CCS map to a main surface cache
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* line pair. The main surface pitch is required to be a multiple of four
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* Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
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* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
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* planes 2 and 3 for the respective CCS.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -593,6 +593,9 @@ struct ethtool_pauseparam {
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* @ETH_SS_RSS_HASH_FUNCS: RSS hush function names
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* @ETH_SS_PHY_STATS: Statistic names, for use with %ETHTOOL_GPHYSTATS
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* @ETH_SS_PHY_TUNABLES: PHY tunable names
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* @ETH_SS_LINK_MODES: link mode names
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* @ETH_SS_MSG_CLASSES: debug message class names
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* @ETH_SS_WOL_MODES: wake-on-lan modes
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*/
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enum ethtool_stringset {
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ETH_SS_TEST = 0,
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@ -604,6 +607,12 @@ enum ethtool_stringset {
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ETH_SS_TUNABLES,
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ETH_SS_PHY_STATS,
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ETH_SS_PHY_TUNABLES,
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ETH_SS_LINK_MODES,
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ETH_SS_MSG_CLASSES,
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ETH_SS_WOL_MODES,
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/* add new constants above here */
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ETH_SS_COUNT
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};
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/**
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@ -1688,6 +1697,8 @@ static inline int ethtool_validate_duplex(uint8_t duplex)
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#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
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#define WAKE_FILTER (1 << 7)
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#define WOL_MODE_COUNT 8
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/* L2-L4 network traffic flow types */
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#define TCP_V4_FLOW 0x01 /* hash or spec (tcp_ip4_spec) */
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#define UDP_V4_FLOW 0x02 /* hash or spec (udp_ip4_spec) */
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@ -31,6 +31,7 @@ struct input_event {
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unsigned long __sec;
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#if defined(__sparc__) && defined(__arch64__)
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unsigned int __usec;
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unsigned int __pad;
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#else
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unsigned long __usec;
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#endif
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@ -676,6 +676,7 @@
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#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
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#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
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#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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@ -390,5 +390,7 @@
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#define __NR_fspick (__NR_SYSCALL_BASE + 433)
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#define __NR_pidfd_open (__NR_SYSCALL_BASE + 434)
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#define __NR_clone3 (__NR_SYSCALL_BASE + 435)
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#define __NR_openat2 (__NR_SYSCALL_BASE + 437)
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#define __NR_pidfd_getfd (__NR_SYSCALL_BASE + 438)
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||||
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#endif /* _ASM_ARM_UNISTD_COMMON_H */
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||||
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@ -220,10 +220,18 @@ struct kvm_vcpu_events {
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#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
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||||
#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
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||||
|
||||
/* EL0 Virtual Timer Registers */
|
||||
/*
|
||||
* EL0 Virtual Timer Registers
|
||||
*
|
||||
* WARNING:
|
||||
* KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
|
||||
* with the appropriate register encodings. Their values have been
|
||||
* accidentally swapped. As this is set API, the definitions here
|
||||
* must be used, rather than ones derived from the encodings.
|
||||
*/
|
||||
#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
|
||||
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
|
||||
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||
|
||||
/* KVM-as-firmware specific pseudo-registers */
|
||||
#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
|
||||
|
||||
@ -19,5 +19,6 @@
|
||||
#define __ARCH_WANT_NEW_STAT
|
||||
#define __ARCH_WANT_SET_GET_RLIMIT
|
||||
#define __ARCH_WANT_TIME32_SYSCALLS
|
||||
#define __ARCH_WANT_SYS_CLONE3
|
||||
|
||||
#include <asm-generic/unistd.h>
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
#define PROT_WRITE 0x2 /* page can be written */
|
||||
#define PROT_EXEC 0x4 /* page can be executed */
|
||||
#define PROT_SEM 0x8 /* page may be used for atomic ops */
|
||||
/* 0x10 reserved for arch-specific use */
|
||||
/* 0x20 reserved for arch-specific use */
|
||||
#define PROT_NONE 0x0 /* page can not be accessed */
|
||||
#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
|
||||
#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
|
||||
|
||||
@ -851,8 +851,13 @@ __SYSCALL(__NR_pidfd_open, sys_pidfd_open)
|
||||
__SYSCALL(__NR_clone3, sys_clone3)
|
||||
#endif
|
||||
|
||||
#define __NR_openat2 437
|
||||
__SYSCALL(__NR_openat2, sys_openat2)
|
||||
#define __NR_pidfd_getfd 438
|
||||
__SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd)
|
||||
|
||||
#undef __NR_syscalls
|
||||
#define __NR_syscalls 436
|
||||
#define __NR_syscalls 439
|
||||
|
||||
/*
|
||||
* 32 bit systems traditionally used different
|
||||
|
||||
@ -365,6 +365,8 @@
|
||||
#define __NR_fspick (__NR_Linux + 433)
|
||||
#define __NR_pidfd_open (__NR_Linux + 434)
|
||||
#define __NR_clone3 (__NR_Linux + 435)
|
||||
#define __NR_openat2 (__NR_Linux + 437)
|
||||
#define __NR_pidfd_getfd (__NR_Linux + 438)
|
||||
|
||||
|
||||
#endif /* _ASM_MIPS_UNISTD_N32_H */
|
||||
|
||||
@ -341,6 +341,8 @@
|
||||
#define __NR_fspick (__NR_Linux + 433)
|
||||
#define __NR_pidfd_open (__NR_Linux + 434)
|
||||
#define __NR_clone3 (__NR_Linux + 435)
|
||||
#define __NR_openat2 (__NR_Linux + 437)
|
||||
#define __NR_pidfd_getfd (__NR_Linux + 438)
|
||||
|
||||
|
||||
#endif /* _ASM_MIPS_UNISTD_N64_H */
|
||||
|
||||
@ -411,6 +411,8 @@
|
||||
#define __NR_fspick (__NR_Linux + 433)
|
||||
#define __NR_pidfd_open (__NR_Linux + 434)
|
||||
#define __NR_clone3 (__NR_Linux + 435)
|
||||
#define __NR_openat2 (__NR_Linux + 437)
|
||||
#define __NR_pidfd_getfd (__NR_Linux + 438)
|
||||
|
||||
|
||||
#endif /* _ASM_MIPS_UNISTD_O32_H */
|
||||
|
||||
@ -418,6 +418,8 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
|
||||
#endif /* _ASM_POWERPC_UNISTD_32_H */
|
||||
|
||||
@ -390,6 +390,8 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
|
||||
#endif /* _ASM_POWERPC_UNISTD_64_H */
|
||||
|
||||
@ -408,5 +408,7 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
#endif /* _ASM_S390_UNISTD_32_H */
|
||||
|
||||
@ -356,5 +356,7 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
#endif /* _ASM_S390_UNISTD_64_H */
|
||||
|
||||
@ -426,5 +426,7 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_32_H */
|
||||
|
||||
@ -348,5 +348,7 @@
|
||||
#define __NR_fspick 433
|
||||
#define __NR_pidfd_open 434
|
||||
#define __NR_clone3 435
|
||||
#define __NR_openat2 437
|
||||
#define __NR_pidfd_getfd 438
|
||||
|
||||
#endif /* _ASM_X86_UNISTD_64_H */
|
||||
|
||||
@ -301,6 +301,8 @@
|
||||
#define __NR_fspick (__X32_SYSCALL_BIT + 433)
|
||||
#define __NR_pidfd_open (__X32_SYSCALL_BIT + 434)
|
||||
#define __NR_clone3 (__X32_SYSCALL_BIT + 435)
|
||||
#define __NR_openat2 (__X32_SYSCALL_BIT + 437)
|
||||
#define __NR_pidfd_getfd (__X32_SYSCALL_BIT + 438)
|
||||
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
|
||||
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
|
||||
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
|
||||
|
||||
@ -1009,6 +1009,7 @@ struct kvm_ppc_resize_hpt {
|
||||
#define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176
|
||||
#define KVM_CAP_ARM_NISV_TO_USER 177
|
||||
#define KVM_CAP_ARM_INJECT_EXT_DABT 178
|
||||
#define KVM_CAP_S390_VCPU_RESETS 179
|
||||
|
||||
#ifdef KVM_CAP_IRQ_ROUTING
|
||||
|
||||
@ -1473,6 +1474,10 @@ struct kvm_enc_region {
|
||||
/* Available with KVM_CAP_ARM_SVE */
|
||||
#define KVM_ARM_VCPU_FINALIZE _IOW(KVMIO, 0xc2, int)
|
||||
|
||||
/* Available with KVM_CAP_S390_VCPU_RESETS */
|
||||
#define KVM_S390_NORMAL_RESET _IO(KVMIO, 0xc3)
|
||||
#define KVM_S390_CLEAR_RESET _IO(KVMIO, 0xc4)
|
||||
|
||||
/* Secure Encrypted Virtualization command */
|
||||
enum sev_cmd_id {
|
||||
/* Guest initialization commands */
|
||||
|
||||
@ -78,13 +78,13 @@ static void s390_cpu_load_normal(CPUState *s)
|
||||
S390CPU *cpu = S390_CPU(s);
|
||||
uint64_t spsw = ldq_phys(s->as, 0);
|
||||
|
||||
cpu->env.psw.mask = spsw & 0xffffffff80000000ULL;
|
||||
cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL;
|
||||
/*
|
||||
* Invert short psw indication, so SIE will report a specification
|
||||
* exception if it was not set.
|
||||
*/
|
||||
cpu->env.psw.mask ^= PSW_MASK_SHORTPSW;
|
||||
cpu->env.psw.addr = spsw & 0x7fffffffULL;
|
||||
cpu->env.psw.addr = spsw & PSW_MASK_SHORT_ADDR;
|
||||
|
||||
s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu);
|
||||
}
|
||||
@ -144,8 +144,18 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
|
||||
}
|
||||
|
||||
/* Reset state inside the kernel that we cannot access yet from QEMU. */
|
||||
if (kvm_enabled() && type != S390_CPU_RESET_NORMAL) {
|
||||
kvm_s390_reset_vcpu(cpu);
|
||||
if (kvm_enabled()) {
|
||||
switch (type) {
|
||||
case S390_CPU_RESET_CLEAR:
|
||||
kvm_s390_reset_vcpu_clear(cpu);
|
||||
break;
|
||||
case S390_CPU_RESET_INITIAL:
|
||||
kvm_s390_reset_vcpu_initial(cpu);
|
||||
break;
|
||||
case S390_CPU_RESET_NORMAL:
|
||||
kvm_s390_reset_vcpu_normal(cpu);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -276,7 +276,8 @@ extern const VMStateDescription vmstate_s390_cpu;
|
||||
#define PSW_MASK_RI 0x0000008000000000ULL
|
||||
#define PSW_MASK_64 0x0000000100000000ULL
|
||||
#define PSW_MASK_32 0x0000000080000000ULL
|
||||
#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
|
||||
#define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
|
||||
#define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
|
||||
|
||||
#undef PSW_ASC_PRIMARY
|
||||
#undef PSW_ASC_ACCREG
|
||||
|
||||
@ -89,7 +89,7 @@ hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
|
||||
static inline bool is_special_wait_psw(uint64_t psw_addr)
|
||||
{
|
||||
/* signal quiesce */
|
||||
return psw_addr == 0xfffUL;
|
||||
return (psw_addr & 0xfffUL) == 0xfffUL;
|
||||
}
|
||||
|
||||
void s390_handle_wait(S390CPU *cpu)
|
||||
|
||||
@ -83,7 +83,15 @@ void kvm_s390_cmma_reset(void)
|
||||
{
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu(S390CPU *cpu)
|
||||
void kvm_s390_reset_vcpu_initial(S390CPU *cpu)
|
||||
{
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu_clear(S390CPU *cpu)
|
||||
{
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu_normal(S390CPU *cpu)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
@ -151,6 +151,7 @@ static int cap_s390_irq;
|
||||
static int cap_ri;
|
||||
static int cap_gs;
|
||||
static int cap_hpage_1m;
|
||||
static int cap_vcpu_resets;
|
||||
|
||||
static int active_cmma;
|
||||
|
||||
@ -342,6 +343,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
|
||||
cap_async_pf = kvm_check_extension(s, KVM_CAP_ASYNC_PF);
|
||||
cap_mem_op = kvm_check_extension(s, KVM_CAP_S390_MEM_OP);
|
||||
cap_s390_irq = kvm_check_extension(s, KVM_CAP_S390_INJECT_IRQ);
|
||||
cap_vcpu_resets = kvm_check_extension(s, KVM_CAP_S390_VCPU_RESETS);
|
||||
|
||||
if (!kvm_check_extension(s, KVM_CAP_S390_GMAP)
|
||||
|| !kvm_check_extension(s, KVM_CAP_S390_COW)) {
|
||||
@ -406,17 +408,41 @@ int kvm_arch_destroy_vcpu(CPUState *cs)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu(S390CPU *cpu)
|
||||
static void kvm_s390_reset_vcpu(S390CPU *cpu, unsigned long type)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
|
||||
/* The initial reset call is needed here to reset in-kernel
|
||||
* vcpu data that we can't access directly from QEMU
|
||||
* (i.e. with older kernels which don't support sync_regs/ONE_REG).
|
||||
* Before this ioctl cpu_synchronize_state() is called in common kvm
|
||||
* code (kvm-all) */
|
||||
if (kvm_vcpu_ioctl(cs, KVM_S390_INITIAL_RESET, NULL)) {
|
||||
error_report("Initial CPU reset failed on CPU %i", cs->cpu_index);
|
||||
/*
|
||||
* The reset call is needed here to reset in-kernel vcpu data that
|
||||
* we can't access directly from QEMU (i.e. with older kernels
|
||||
* which don't support sync_regs/ONE_REG). Before this ioctl
|
||||
* cpu_synchronize_state() is called in common kvm code
|
||||
* (kvm-all).
|
||||
*/
|
||||
if (kvm_vcpu_ioctl(cs, type)) {
|
||||
error_report("CPU reset failed on CPU %i type %lx",
|
||||
cs->cpu_index, type);
|
||||
}
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu_initial(S390CPU *cpu)
|
||||
{
|
||||
kvm_s390_reset_vcpu(cpu, KVM_S390_INITIAL_RESET);
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu_clear(S390CPU *cpu)
|
||||
{
|
||||
if (cap_vcpu_resets) {
|
||||
kvm_s390_reset_vcpu(cpu, KVM_S390_CLEAR_RESET);
|
||||
} else {
|
||||
kvm_s390_reset_vcpu(cpu, KVM_S390_INITIAL_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
void kvm_s390_reset_vcpu_normal(S390CPU *cpu)
|
||||
{
|
||||
if (cap_vcpu_resets) {
|
||||
kvm_s390_reset_vcpu(cpu, KVM_S390_NORMAL_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -34,7 +34,9 @@ int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
|
||||
int vq, bool assign);
|
||||
int kvm_s390_cmma_active(void);
|
||||
void kvm_s390_cmma_reset(void);
|
||||
void kvm_s390_reset_vcpu(S390CPU *cpu);
|
||||
void kvm_s390_reset_vcpu_clear(S390CPU *cpu);
|
||||
void kvm_s390_reset_vcpu_normal(S390CPU *cpu);
|
||||
void kvm_s390_reset_vcpu_initial(S390CPU *cpu);
|
||||
int kvm_s390_set_mem_limit(uint64_t new_limit, uint64_t *hw_limit);
|
||||
void kvm_s390_set_max_pagesize(uint64_t pagesize, Error **errp);
|
||||
void kvm_s390_crypto_reset(void);
|
||||
|
||||
@ -3874,7 +3874,7 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
|
||||
|
||||
/* Operate. */
|
||||
switch (s->fields.op2) {
|
||||
case 0x55: /* AND */
|
||||
case 0x54: /* AND */
|
||||
tcg_gen_ori_i64(o->in2, o->in2, ~mask);
|
||||
tcg_gen_and_i64(o->out, o->out, o->in2);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user