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target/arm: Convert Extract instructions to decodetree

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Convert the EXTR instruction to decodetree (this is the
only one in the 'Extract" class). This is the last of
the dp-immediate insns in the legacy decoder, so we
can now remove disas_data_proc_imm().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-05-12 15:40:58 +01:00
parent 5e451ae63b
commit 4240fb6175
2 changed files with 36 additions and 65 deletions
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7
target/arm/tcg/a64.decode
View File

@ -97,3 +97,10 @@ BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
# Extract
&extract rd rn rm imm sf
EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0

68
target/arm/tcg/translate-a64.c
View File

@ -4530,77 +4530,44 @@ static bool trans_BFM(DisasContext *s, arg_BFM *a)
return true;
}
/* Extract
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
* +----+------+-------------+---+----+------+--------+------+------+
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
* +----+------+-------------+---+----+------+--------+------+------+
*/
static void disas_extract(DisasContext *s, uint32_t insn)
static bool trans_EXTR(DisasContext *s, arg_extract *a)
{
unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
sf = extract32(insn, 31, 1);
n = extract32(insn, 22, 1);
rm = extract32(insn, 16, 5);
imm = extract32(insn, 10, 6);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
op21 = extract32(insn, 29, 2);
op0 = extract32(insn, 21, 1);
bitsize = sf ? 64 : 32;
if (sf != n || op21 || op0 || imm >= bitsize) {
unallocated_encoding(s);
} else {
TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
tcg_rd = cpu_reg(s, rd);
tcg_rd = cpu_reg(s, a->rd);
if (unlikely(imm == 0)) {
/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
if (unlikely(a->imm == 0)) {
/*
* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
* so an extract from bit 0 is a special case.
*/
if (sf) {
tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
if (a->sf) {
tcg_gen_mov_i64(tcg_rd, cpu_reg(s, a->rm));
} else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, a->rm));
}
} else {
tcg_rm = cpu_reg(s, rm);
tcg_rn = cpu_reg(s, rn);
tcg_rm = cpu_reg(s, a->rm);
tcg_rn = cpu_reg(s, a->rn);
if (sf) {
if (a->sf) {
/* Specialization to ROR happens in EXTRACT2. */
tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, a->imm);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t0, tcg_rm);
if (rm == rn) {
tcg_gen_rotri_i32(t0, t0, imm);
if (a->rm == a->rn) {
tcg_gen_rotri_i32(t0, t0, a->imm);
} else {
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t1, tcg_rn);
tcg_gen_extract2_i32(t0, t0, t1, imm);
tcg_gen_extract2_i32(t0, t0, t1, a->imm);
}
tcg_gen_extu_i32_i64(tcg_rd, t0);
}
}
}
}
/* Data processing - immediate */
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 23, 6)) {
case 0x27: /* Extract */
disas_extract(s, insn);
break;
default:
unallocated_encoding(s);
break;
}
return true;
}
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
@ -14125,9 +14092,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
static void disas_a64_legacy(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 4)) {
case 0x8: case 0x9: /* Data processing - immediate */
disas_data_proc_imm(s, insn);
break;
case 0xa: case 0xb: /* Branch, exception generation and system insns */
disas_b_exc_sys(s, insn);
break;