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target/mips: Refactor and fix COPY_U.<B|H|W> instructions

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The old version of the helper for the COPY_U.<B|H|W> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
This commit is contained in:
Mateja Marjanovic 2019-04-02 15:43:24 +02:00 committed by Aleksandar Markovic
parent 631c467461
commit 41d2885827
3 changed files with 61 additions and 23 deletions
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4
target/mips/helper.h
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@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
@ -942,6 +941,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)

59
target/mips/msa_helper.c
View File

@ -1298,29 +1298,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n]; env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
} }
void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n) uint32_t ws, uint32_t n)
{ {
n %= DF_ELEMENTS(df); n %= 16;
#if defined(HOST_WORDS_BIGENDIAN)
switch (df) { if (n < 8) {
case DF_BYTE: n = 8 - n - 1;
env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; } else {
break; n = 24 - n - 1;
case DF_HALF:
env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
break;
case DF_WORD:
env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
break;
#ifdef TARGET_MIPS64
case DF_DOUBLE:
env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
break;
#endif
default:
assert(0);
} }
#endif
env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
}
void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= 8;
#if defined(HOST_WORDS_BIGENDIAN)
if (n < 4) {
n = 4 - n - 1;
} else {
n = 12 - n - 1;
}
#endif
env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
}
void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= 4;
#if defined(HOST_WORDS_BIGENDIAN)
if (n < 2) {
n = 2 - n - 1;
} else {
n = 6 - n - 1;
}
#endif
env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
} }
void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,

21
target/mips/translate.c
View File

@ -28297,6 +28297,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
} }
if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
(df == DF_WORD)) {
generate_exception_end(ctx, EXCP_RI);
break;
}
#endif #endif
switch (MASK_MSA_ELM(ctx->opcode)) { switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df: case OPC_COPY_S_df:
@ -28323,7 +28328,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
break; break;
case OPC_COPY_U_df: case OPC_COPY_U_df:
if (likely(wd != 0)) { if (likely(wd != 0)) {
gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); switch (df) {
case DF_BYTE:
gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
break;
case DF_HALF:
gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
break;
#if defined(TARGET_MIPS64)
case DF_WORD:
gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);
}
} }
break; break;
case OPC_INSERT_df: case OPC_INSERT_df: