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target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:37 -07:00 committed by Peter Maydell
parent 93b7b9057d
commit 41c34bccc2
2 changed files with 10 additions and 16 deletions
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4
target/arm/tcg/a64.decode
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@ -918,6 +918,10 @@ SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
### Advanced SIMD scalar x indexed element

22
target/arm/tcg/translate-a64.c
View File

@ -5460,6 +5460,10 @@ TRANS(SHSUB_v, do_gvec_fn3_no64, a, gen_gvec_shsub)
TRANS(UHSUB_v, do_gvec_fn3_no64, a, gen_gvec_uhsub)
TRANS(SRHADD_v, do_gvec_fn3_no64, a, gen_gvec_srhadd)
TRANS(URHADD_v, do_gvec_fn3_no64, a, gen_gvec_urhadd)
TRANS(SMAX_v, do_gvec_fn3_no64, a, tcg_gen_gvec_smax)
TRANS(UMAX_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umax)
TRANS(SMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_smin)
TRANS(UMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umin)
static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
{
@ -10925,8 +10929,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
return;
}
/* fall through */
case 0xc: /* SMAX, UMAX */
case 0xd: /* SMIN, UMIN */
case 0xe: /* SABD, UABD */
case 0xf: /* SABA, UABA */
case 0x12: /* MLA, MLS */
@ -10959,6 +10961,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
case 0x09: /* SQSHL, UQSHL */
case 0x0a: /* SRSHL, URSHL */
case 0x0b: /* SQRSHL, UQRSHL */
case 0x0c: /* SMAX, UMAX */
case 0x0d: /* SMIN, UMIN */
case 0x10: /* ADD, SUB */
case 0x11: /* CMTST, CMEQ */
unallocated_encoding(s);
@ -10970,20 +10974,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
}
switch (opcode) {
case 0x0c: /* SMAX, UMAX */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size);
}
return;
case 0x0d: /* SMIN, UMIN */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size);
}
return;
case 0xe: /* SABD, UABD */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size);