MIPS FPU fixes (Daniel Jacobowitz).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2213 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -799,7 +799,7 @@ FLOAT_OP(cvtd, w)
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}
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FLOAT_OP(cvts, d)
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{
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FST2 = float64_to_float32(WT0, &env->fp_status);
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FST2 = float64_to_float32(FDT0, &env->fp_status);
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DEBUG_FPU_STATE();
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RETURN();
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}
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@ -1791,7 +1791,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int
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break;
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case FOP(32, 17): /* cvt.s.d */
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CHECK_FR(ctx, fs | fd);
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GEN_LOAD_FREG_FTN(WT0, fs);
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GEN_LOAD_FREG_FTN(DT0, fs);
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gen_op_float_cvts_d();
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GEN_STORE_FTN_FREG(fd, WT2);
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opn = "cvt.s.d";
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@ -1812,7 +1812,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int
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break;
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case FOP(36, 17): /* cvt.w.d */
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CHECK_FR(ctx, fs | fd);
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GEN_LOAD_FREG_FTN(WT0, fs);
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GEN_LOAD_FREG_FTN(DT0, fs);
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gen_op_float_cvtw_d();
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GEN_STORE_FTN_FREG(fd, WT2);
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opn = "cvt.w.d";
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@ -2089,6 +2089,7 @@ static void decode_opc (DisasContext *ctx)
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case 0x39: /* SWC1 */
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case 0x3D: /* SDC1 */
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#if defined(MIPS_USES_FPU)
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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gen_flt_ldst(ctx, op, rt, rs, imm);
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#else
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@ -2098,6 +2099,7 @@ static void decode_opc (DisasContext *ctx)
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case 0x11: /* CP1 opcode */
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#if defined(MIPS_USES_FPU)
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save_cpu_state(ctx, 1);
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gen_op_cp1_enabled();
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op1 = ((ctx->opcode >> 21) & 0x1F);
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switch (op1) {
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