accel/tcg: Trigger watchpoints from atomic_mmu_lookup
Fixes a bug in that we weren't reporting these changes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1767,6 +1767,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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CPUTLBEntry *tlbe;
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target_ulong tlb_addr;
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void *hostaddr;
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CPUTLBEntryFull *full;
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tcg_debug_assert(mmu_idx < NB_MMU_MODES);
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@ -1805,17 +1806,26 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
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}
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/* Let the guest notice RMW on a write-only page. */
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if ((prot & PAGE_READ) &&
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unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {
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tlb_fill(env_cpu(env), addr, size,
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MMU_DATA_LOAD, mmu_idx, retaddr);
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if (prot & PAGE_READ) {
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/*
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* Since we don't support reads and writes to different addresses,
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* and we do have the proper page loaded for write, this shouldn't
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* ever return. But just in case, handle via stop-the-world.
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* Let the guest notice RMW on a write-only page.
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* We have just verified that the page is writable.
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* Subpage lookups may have left TLB_INVALID_MASK set,
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* but addr_read will only be -1 if PAGE_READ was unset.
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*/
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goto stop_the_world;
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if (unlikely(tlbe->addr_read == -1)) {
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tlb_fill(env_cpu(env), addr, size,
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MMU_DATA_LOAD, mmu_idx, retaddr);
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/*
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* Since we don't support reads and writes to different
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* addresses, and we do have the proper page loaded for
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* write, this shouldn't ever return. But just in case,
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* handle via stop-the-world.
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*/
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goto stop_the_world;
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}
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/* Collect TLB_WATCHPOINT for read. */
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tlb_addr |= tlbe->addr_read;
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}
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} else /* if (prot & PAGE_READ) */ {
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tlb_addr = tlbe->addr_read;
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@ -1838,10 +1848,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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}
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hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
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full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
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if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
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notdirty_write(env_cpu(env), addr, size,
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&env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr);
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notdirty_write(env_cpu(env), addr, size, full, retaddr);
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}
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if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
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QEMU_BUILD_BUG_ON(PAGE_READ != BP_MEM_READ);
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QEMU_BUILD_BUG_ON(PAGE_WRITE != BP_MEM_WRITE);
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/* therefore prot == watchpoint bits */
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cpu_check_watchpoint(env_cpu(env), addr, size,
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full->attrs, prot, retaddr);
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}
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return hostaddr;
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