hw/riscv: Move sifive_clint model to hw/intc

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-09-03 18:40:16 +08:00 committed by Alistair Francis
parent 4921a0ce86
commit 406fafd5d0
11 changed files with 15 additions and 7 deletions

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@ -67,3 +67,6 @@ config RX_ICU
config LOONGSON_LIOINTC config LOONGSON_LIOINTC
bool bool
config SIFIVE_CLINT
bool

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@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c')) specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c')) specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c')) specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))

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@ -26,7 +26,7 @@
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "hw/riscv/sifive_clint.h" #include "hw/intc/sifive_clint.h"
#include "qemu/timer.h" #include "qemu/timer.h"
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)

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@ -15,6 +15,7 @@ config SIFIVE_E
bool bool
select HART select HART
select SIFIVE select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO select SIFIVE_GPIO
select SIFIVE_E_PRCI select SIFIVE_E_PRCI
select UNIMP select UNIMP
@ -24,6 +25,7 @@ config SIFIVE_U
select CADENCE select CADENCE
select HART select HART
select SIFIVE select SIFIVE
select SIFIVE_CLINT
select SIFIVE_GPIO select SIFIVE_GPIO
select SIFIVE_PDMA select SIFIVE_PDMA
select SIFIVE_U_OTP select SIFIVE_U_OTP
@ -35,6 +37,7 @@ config SPIKE
select HART select HART
select HTIF select HTIF
select SIFIVE select SIFIVE
select SIFIVE_CLINT
config OPENTITAN config OPENTITAN
bool bool
@ -54,11 +57,13 @@ config RISCV_VIRT
select PCI_EXPRESS_GENERIC_BRIDGE select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01 select PFLASH_CFI01
select SIFIVE select SIFIVE
select SIFIVE_CLINT
config MICROCHIP_PFSOC config MICROCHIP_PFSOC
bool bool
select HART select HART
select SIFIVE select SIFIVE
select SIFIVE_CLINT
select UNIMP select UNIMP
select MCHP_PFSOC_MMUART select MCHP_PFSOC_MMUART
select SIFIVE_PDMA select SIFIVE_PDMA

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@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))

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@ -48,9 +48,9 @@
#include "hw/misc/unimp.h" #include "hw/misc/unimp.h"
#include "hw/riscv/boot.h" #include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h" #include "hw/riscv/microchip_pfsoc.h"
#include "hw/intc/sifive_clint.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
/* /*

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@ -40,10 +40,10 @@
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h" #include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h" #include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
#include "hw/misc/sifive_e_prci.h" #include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h" #include "chardev/char.h"
#include "sysemu/arch_init.h" #include "sysemu/arch_init.h"

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@ -47,10 +47,10 @@
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_u.h" #include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h" #include "hw/riscv/boot.h"
#include "hw/intc/sifive_clint.h"
#include "chardev/char.h" #include "chardev/char.h"
#include "net/eth.h" #include "net/eth.h"
#include "sysemu/arch_init.h" #include "sysemu/arch_init.h"

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@ -33,10 +33,10 @@
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/riscv/riscv_htif.h" #include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/spike.h" #include "hw/riscv/spike.h"
#include "hw/riscv/boot.h" #include "hw/riscv/boot.h"
#include "hw/riscv/numa.h" #include "hw/riscv/numa.h"
#include "hw/intc/sifive_clint.h"
#include "chardev/char.h" #include "chardev/char.h"
#include "sysemu/arch_init.h" #include "sysemu/arch_init.h"
#include "sysemu/device_tree.h" #include "sysemu/device_tree.h"

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@ -31,11 +31,11 @@
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_test.h" #include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h" #include "hw/riscv/virt.h"
#include "hw/riscv/boot.h" #include "hw/riscv/boot.h"
#include "hw/riscv/numa.h" #include "hw/riscv/numa.h"
#include "hw/intc/sifive_clint.h"
#include "chardev/char.h" #include "chardev/char.h"
#include "sysemu/arch_init.h" #include "sysemu/arch_init.h"
#include "sysemu/device_tree.h" #include "sysemu/device_tree.h"