mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add SuperSPARC MMU breakpoint registers (Robert Reif)

Browse Source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-12-23 15:30:50 +00:00
parent 0bb3602c44
commit 4017190e2d
2 changed files with 45 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target-sparc/cpu.h
View File

@ -301,6 +301,7 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[32]; uint32_t mmuregs[32];
uint64_t mxccdata[4]; uint64_t mxccdata[4];
uint64_t mxccregs[8]; uint64_t mxccregs[8];
uint64_t mmubpregs[4];
uint64_t prom_addr; uint64_t prom_addr;
#endif #endif
/* temporary float registers */ /* temporary float registers */

45
target-sparc/op_helper.c
View File

@ -953,6 +953,28 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x39: /* data cache diagnostic register */ case 0x39: /* data cache diagnostic register */
ret = 0; ret = 0;
break; break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
{
int reg = (addr >> 8) & 3;
switch(reg) {
case 0: /* Breakpoint Value (Addr) */
ret = env->mmubpregs[reg];
break;
case 1: /* Breakpoint Mask */
ret = env->mmubpregs[reg];
break;
case 2: /* Breakpoint Control */
ret = env->mmubpregs[reg];
break;
case 3: /* Breakpoint Status */
ret = env->mmubpregs[reg];
env->mmubpregs[reg] = 0ULL;
break;
}
DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
}
break;
case 8: /* User code access, XXX */ case 8: /* User code access, XXX */
default: default:
do_unassigned_access(addr, 0, 0, asi, size); do_unassigned_access(addr, 0, 0, asi, size);
@ -1283,9 +1305,30 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
// descriptor diagnostic // descriptor diagnostic
case 0x36: /* I-cache flash clear */ case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */ case 0x37: /* D-cache flash clear */
case 0x38: /* breakpoint diagnostics */
case 0x4c: /* breakpoint action */ case 0x4c: /* breakpoint action */
break; break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
int reg = (addr >> 8) & 3;
switch(reg) {
case 0: /* Breakpoint Value (Addr) */
env->mmubpregs[reg] = (val & 0xfffffffffULL);
break;
case 1: /* Breakpoint Mask */
env->mmubpregs[reg] = (val & 0xfffffffffULL);
break;
case 2: /* Breakpoint Control */
env->mmubpregs[reg] = (val & 0x7fULL);
break;
case 3: /* Breakpoint Status */
env->mmubpregs[reg] = (val & 0xfULL);
break;
}
DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
env->mmuregs[reg]);
}
break;
case 8: /* User code access, XXX */ case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */ case 9: /* Supervisor code access, XXX */
default: default: