mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/riscv: remove RISCV_FEATURE_PMP

Browse Source 
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
cpu->cfg.pmp flag. Use the flag instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-02-22 15:52:02 -03:00 committed by Palmer Dabbelt
parent 6a3ffda2ba
commit 3fe40ef5a9
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
7 changed files with 5 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/riscv/cpu.c
View File

@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
riscv_set_feature(env, RISCV_FEATURE_PMP);
}
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available

1
target/riscv/cpu.h
View File

@ -87,7 +87,6 @@
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
};
/* Privileged specification version */

2
target/riscv/cpu_helper.c
View File

@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
pmp_priv_t pmp_priv;
int pmp_index = -1;
if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
if (!riscv_cpu_cfg(env)->pmp) {
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}

2
target/riscv/csr.c
View File

@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
static RISCVException pmp(CPURISCVState *env, int csrno)
{
if (riscv_feature(env, RISCV_FEATURE_PMP)) {
if (riscv_cpu_cfg(env)->pmp) {
return RISCV_EXCP_NONE;
}

3
target/riscv/machine.c
View File

@ -27,9 +27,8 @@
static bool pmp_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
return riscv_feature(env, RISCV_FEATURE_PMP);
return cpu->cfg.pmp;
}
static int pmp_post_load(void *opaque, int version_id)

2
target/riscv/op_helper.c
View File

@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
if (riscv_cpu_cfg(env)->pmp &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}

2
target/riscv/pmp.c
View File

@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
}
}
if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
/*
* Privileged spec v1.10 states if HW doesn't implement any PMP entry
* or no PMP entry matches an M-Mode access, the access succeeds.