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target-mips: fix xtlb exception for loongson

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Loongson 2E and 2F use the same entry for xtlb and tlb exception, at
offset 0x000.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2010-07-15 23:13:11 +02:00
parent 08218b3527
commit 3fc00a7bde
1 changed files with 4 additions and 2 deletions
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6
target-mips/helper.c
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@ -491,7 +491,8 @@ void do_interrupt (CPUState *env)
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
offset = 0x080; offset = 0x080;
else else
#endif #endif
@ -507,7 +508,8 @@ void do_interrupt (CPUState *env)
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
(!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
offset = 0x080; offset = 0x080;
else else
#endif #endif