mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target-tricore: Add instructions of BOL opcode format

Browse Source 
Add instructions of BOL opcode format.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2014-10-16 21:07:29 +01:00
parent 7fb8da2b88
commit 3fb763cb55
2 changed files with 51 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
target-tricore/translate.c
View File

@ -2279,6 +2279,46 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
tcg_temp_free(temp3); tcg_temp_free(temp3);
} }
static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
{
int r1, r2;
int32_t address;
TCGv temp;
r1 = MASK_OP_BOL_S1D(ctx->opcode);
r2 = MASK_OP_BOL_S2(ctx->opcode);
address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
switch (op1) {
case OPC1_32_BOL_LD_A_LONGOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
case OPC1_32_BOL_LD_W_LONFOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
case OPC1_32_BOL_LEA_LONGOFF:
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
break;
case OPC1_32_BOL_ST_A_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
/* raise illegal opcode trap */
}
break;
case OPC1_32_BOL_ST_W_LONGOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
}
}
static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
{ {
int op1; int op1;
@ -2405,6 +2445,14 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
break; break;
/* BOL-format */
case OPC1_32_BOL_LD_A_LONGOFF:
case OPC1_32_BOL_LD_W_LONFOFF:
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
decode_bol_opc(env, ctx, op1);
break;
} }
} }

4
target-tricore/tricore-opcodes.h
View File

@ -115,7 +115,9 @@
#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \ #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \ (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
(MASK_BITS_SHIFT(op, 22, 27) >> 10)) (MASK_BITS_SHIFT(op, 22, 27) >> 10))
#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
(MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
#define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15) #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
#define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11) #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)