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Xtensa fixes:

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- add 64-bit floating point registers;
 - fix gdb register map construction.
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Merge remote-tracking branch 'remotes/xtensa/tags/20150706-xtensa' into staging

Xtensa fixes:

- add 64-bit floating point registers;
- fix gdb register map construction.

# gpg: Signature made Mon Jul  6 11:27:45 2015 BST using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20150706-xtensa:
  target-xtensa: fix gdb register map construction
  target-xtensa: add 64-bit floating point registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-07-06 12:51:51 +01:00
commit 3fa18bc9a5
9 changed files with 70 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-xtensa/core-dc232b.c
View File

@ -33,7 +33,7 @@
#include "core-dc232b/core-isa.h"
#include "overlay_tool.h"
static const XtensaConfig dc232b __attribute__((unused)) = {
static XtensaConfig dc232b __attribute__((unused)) = {
.name = "dc232b",
.gdb_regmap = {
.num_regs = 120,

2
target-xtensa/core-dc233c.c
View File

@ -34,7 +34,7 @@
#include "core-dc233c/core-isa.h"
#include "overlay_tool.h"
static const XtensaConfig dc233c __attribute__((unused)) = {
static XtensaConfig dc233c __attribute__((unused)) = {
.name = "dc233c",
.gdb_regmap = {
.num_regs = 121,

7
target-xtensa/core-fsf.c
View File

@ -33,9 +33,14 @@
#include "core-fsf/core-isa.h"
#include "overlay_tool.h"
static const XtensaConfig fsf __attribute__((unused)) = {
static XtensaConfig fsf __attribute__((unused)) = {
.name = "fsf",
.gdb_regmap = {
/* GDB for this core is not supported currently */
.reg = {
XTREG_END
},
},
.clock_freq_khz = 10000,
DEFAULT_SECTIONS
};

19
target-xtensa/cpu.h
View File

@ -287,6 +287,7 @@ typedef struct XtensaGdbReg {
int targno;
int type;
int group;
unsigned size;
} XtensaGdbReg;
typedef struct XtensaGdbRegmap {
@ -336,6 +337,18 @@ typedef struct XtensaConfigList {
struct XtensaConfigList *next;
} XtensaConfigList;
#ifdef HOST_WORDS_BIGENDIAN
enum {
FP_F32_HIGH,
FP_F32_LOW,
};
#else
enum {
FP_F32_LOW,
FP_F32_HIGH,
};
#endif
typedef struct CPUXtensaState {
const XtensaConfig *config;
uint32_t regs[16];
@ -343,7 +356,10 @@ typedef struct CPUXtensaState {
uint32_t sregs[256];
uint32_t uregs[256];
uint32_t phys_regs[MAX_NAREG];
float32 fregs[16];
union {
float32 f32[2];
float64 f64;
} fregs[16];
float_status fp_status;
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
@ -384,6 +400,7 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model);
void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);

25
target-xtensa/gdbstub.c
View File

@ -26,6 +26,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
unsigned i;
if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
return 0;
@ -47,8 +48,16 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
case 4: /*f*/
return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno
& 0x0f]));
i = reg->targno & 0x0f;
switch (reg->size) {
case 4:
return gdb_get_reg32(mem_buf,
float32_val(env->fregs[i].f32[FP_F32_LOW]));
case 8:
return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
default:
return 0;
}
case 8: /*a*/
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
@ -92,8 +101,16 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
case 4: /*f*/
env->fregs[reg->targno & 0x0f] = make_float32(tmp);
break;
switch (reg->size) {
case 4:
env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
return 4;
case 8:
env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
return 8;
default:
return 0;
}
case 8: /*a*/
env->regs[reg->targno & 0x0f] = tmp;

14
target-xtensa/helper.c
View File

@ -51,6 +51,20 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
}
void xtensa_finalize_config(XtensaConfig *config)
{
unsigned i, n = 0;
if (config->gdb_regmap.num_regs) {
return;
}
for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
n += (config->gdb_regmap.reg[i].type != 6);
}
config->gdb_regmap.num_regs = n;
}
void xtensa_register_core(XtensaConfigList *node)
{
TypeInfo type = {

6
target-xtensa/import_core.sh
View File

@ -22,8 +22,7 @@ mkdir -p "$TARGET"
tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
--xform='s/core/core-isa/' config/core.h
tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
sed -n '1,/*\//p;/pc/,/a15/p' > "$TARGET"/gdb-config.c
NUM_REGS=$(grep XTREG "$TARGET"/gdb-config.c | wc -l)
sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
cat <<EOF > "${TARGET}.c"
#include "cpu.h"
@ -34,10 +33,9 @@ cat <<EOF > "${TARGET}.c"
#include "core-$NAME/core-isa.h"
#include "overlay_tool.h"
static const XtensaConfig $NAME __attribute__((unused)) = {
static XtensaConfig $NAME __attribute__((unused)) = {
.name = "$NAME",
.gdb_regmap = {
.num_regs = $NUM_REGS,
.reg = {
#include "core-$NAME/gdb-config.c"
}

4
target-xtensa/overlay_tool.h
View File

@ -27,7 +27,8 @@
#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
a1, a2, a3, a4, a5, a6) \
{ .targno = (no), .type = (typ), .group = (grp) },
{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
#define XTREG_END { .targno = -1 },
#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
@ -316,6 +317,7 @@
static XtensaConfigList node = { \
.config = &core, \
}; \
xtensa_finalize_config(&core); \
xtensa_register_core(&node); \
}
#else

7
target-xtensa/translate.c
View File

@ -228,7 +228,7 @@ void xtensa_translate_init(void)
for (i = 0; i < 16; i++) {
cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUXtensaState, fregs[i]),
offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
fregnames[i]);
}
@ -3206,8 +3206,9 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
for (i = 0; i < 16; ++i) {
cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
float32_val(env->fregs[i]),
*(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
float32_val(env->fregs[i].f32[FP_F32_LOW]),
*(float *)(env->fregs[i].f32 + FP_F32_LOW),
(i % 2) == 1 ? '\n' : ' ');
}
}
}