Xtensa fixes:
- add 64-bit floating point registers; - fix gdb register map construction. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVmlghAAoJEFH5zJH4P6BEuN4QAIj8n7LGBy4Sj+IY24W/YvOu ZPBiuqgQ8jyGAKyJ/dF36ujSRB1f05AnO2c5mfZy04m1iV6B60nH2jfOq9L9PxCF dcpQY2WUjTPyiI+8iFHeQlNCqwFuMXcgpBXfu/B9DN1KcXyHBOWJe6p2qcrxdq5o 7F5NJtxLe+5r2/SAkVB9b2ZHU98/ZeL+CeYb4lju83u7CM7AcddLmh25EkVh2nyO rqT53RAdE4PpQ5zIa2YMrC2yY9cTbj8vfLg2GLF+IIKPtADksnlqdlxs9hDbn4Zs 4tjNZRK+7tObc/3xoOE9IX30yqdU12lfzIEz4i1qInLD4Xqdg7R710G39peiHo4q /U8L62vGgSG14LuMLb8cOSCsgoxvqaq7UbrSxTIy2x2tYKkRLJO7wYacS/7QFBL/ nPBPUASJJibUQdeNB+16lx94xORwRQwlnP8wsuf5+aefiAoWd12ybbKluCGneK1M jsL+W3+P1yHi/x9T0Rs6idlIo3TD2Aa0+Mmnp13izwfv59/8mtrLh48zIqIIFvkT 75twVKavdHbnhnZDUytVdfw7EwQ/GfXP5E88pqMoEc7tIA7lC9MZ/hDHWHvdal30 /8NgRwcnRXFDnSEyxE2OTOzuCPUKjw1xhvAtK5jX0SxBtIvll7jMOnOlHJu0s3Ls 1+vX2J4Derf4U1C2Q9zO =Huqr -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20150706-xtensa' into staging Xtensa fixes: - add 64-bit floating point registers; - fix gdb register map construction. # gpg: Signature made Mon Jul 6 11:27:45 2015 BST using RSA key ID F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" * remotes/xtensa/tags/20150706-xtensa: target-xtensa: fix gdb register map construction target-xtensa: add 64-bit floating point registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
3fa18bc9a5
@ -33,7 +33,7 @@
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#include "core-dc232b/core-isa.h"
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#include "core-dc232b/core-isa.h"
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#include "overlay_tool.h"
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#include "overlay_tool.h"
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static const XtensaConfig dc232b __attribute__((unused)) = {
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static XtensaConfig dc232b __attribute__((unused)) = {
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.name = "dc232b",
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.name = "dc232b",
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.gdb_regmap = {
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.gdb_regmap = {
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.num_regs = 120,
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.num_regs = 120,
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@ -34,7 +34,7 @@
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#include "core-dc233c/core-isa.h"
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#include "core-dc233c/core-isa.h"
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#include "overlay_tool.h"
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#include "overlay_tool.h"
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static const XtensaConfig dc233c __attribute__((unused)) = {
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static XtensaConfig dc233c __attribute__((unused)) = {
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.name = "dc233c",
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.name = "dc233c",
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.gdb_regmap = {
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.gdb_regmap = {
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.num_regs = 121,
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.num_regs = 121,
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@ -33,9 +33,14 @@
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#include "core-fsf/core-isa.h"
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#include "core-fsf/core-isa.h"
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#include "overlay_tool.h"
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#include "overlay_tool.h"
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static const XtensaConfig fsf __attribute__((unused)) = {
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static XtensaConfig fsf __attribute__((unused)) = {
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.name = "fsf",
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.name = "fsf",
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.gdb_regmap = {
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/* GDB for this core is not supported currently */
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/* GDB for this core is not supported currently */
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.reg = {
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XTREG_END
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},
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},
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.clock_freq_khz = 10000,
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.clock_freq_khz = 10000,
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DEFAULT_SECTIONS
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DEFAULT_SECTIONS
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};
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};
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@ -287,6 +287,7 @@ typedef struct XtensaGdbReg {
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int targno;
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int targno;
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int type;
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int type;
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int group;
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int group;
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unsigned size;
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} XtensaGdbReg;
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} XtensaGdbReg;
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typedef struct XtensaGdbRegmap {
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typedef struct XtensaGdbRegmap {
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@ -336,6 +337,18 @@ typedef struct XtensaConfigList {
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struct XtensaConfigList *next;
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struct XtensaConfigList *next;
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} XtensaConfigList;
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} XtensaConfigList;
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#ifdef HOST_WORDS_BIGENDIAN
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enum {
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FP_F32_HIGH,
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FP_F32_LOW,
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};
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#else
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enum {
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FP_F32_LOW,
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FP_F32_HIGH,
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};
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#endif
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typedef struct CPUXtensaState {
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typedef struct CPUXtensaState {
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const XtensaConfig *config;
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const XtensaConfig *config;
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uint32_t regs[16];
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uint32_t regs[16];
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@ -343,7 +356,10 @@ typedef struct CPUXtensaState {
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uint32_t sregs[256];
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uint32_t sregs[256];
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uint32_t uregs[256];
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uint32_t uregs[256];
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uint32_t phys_regs[MAX_NAREG];
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uint32_t phys_regs[MAX_NAREG];
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float32 fregs[16];
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union {
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float32 f32[2];
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float64 f64;
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} fregs[16];
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float_status fp_status;
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float_status fp_status;
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xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
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xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
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@ -384,6 +400,7 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model);
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void xtensa_translate_init(void);
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void xtensa_translate_init(void);
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void xtensa_breakpoint_handler(CPUState *cs);
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void xtensa_breakpoint_handler(CPUState *cs);
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int cpu_xtensa_exec(CPUXtensaState *s);
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int cpu_xtensa_exec(CPUXtensaState *s);
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void xtensa_finalize_config(XtensaConfig *config);
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void xtensa_register_core(XtensaConfigList *node);
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void xtensa_register_core(XtensaConfigList *node);
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void check_interrupts(CPUXtensaState *s);
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void check_interrupts(CPUXtensaState *s);
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void xtensa_irq_init(CPUXtensaState *env);
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void xtensa_irq_init(CPUXtensaState *env);
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@ -26,6 +26,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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XtensaCPU *cpu = XTENSA_CPU(cs);
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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CPUXtensaState *env = &cpu->env;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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unsigned i;
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if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
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if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
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return 0;
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return 0;
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@ -47,8 +48,16 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
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return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
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case 4: /*f*/
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case 4: /*f*/
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return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno
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i = reg->targno & 0x0f;
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& 0x0f]));
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switch (reg->size) {
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case 4:
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return gdb_get_reg32(mem_buf,
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float32_val(env->fregs[i].f32[FP_F32_LOW]));
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case 8:
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return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
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default:
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return 0;
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}
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case 8: /*a*/
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case 8: /*a*/
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return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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@ -92,8 +101,16 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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break;
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break;
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case 4: /*f*/
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case 4: /*f*/
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env->fregs[reg->targno & 0x0f] = make_float32(tmp);
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switch (reg->size) {
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break;
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case 4:
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env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
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return 4;
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case 8:
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env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
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return 8;
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default:
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return 0;
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}
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case 8: /*a*/
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case 8: /*a*/
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env->regs[reg->targno & 0x0f] = tmp;
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env->regs[reg->targno & 0x0f] = tmp;
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@ -51,6 +51,20 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data)
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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}
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}
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void xtensa_finalize_config(XtensaConfig *config)
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{
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unsigned i, n = 0;
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if (config->gdb_regmap.num_regs) {
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return;
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}
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for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
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n += (config->gdb_regmap.reg[i].type != 6);
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}
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config->gdb_regmap.num_regs = n;
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}
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void xtensa_register_core(XtensaConfigList *node)
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void xtensa_register_core(XtensaConfigList *node)
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{
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{
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TypeInfo type = {
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TypeInfo type = {
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@ -22,8 +22,7 @@ mkdir -p "$TARGET"
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tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
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tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
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--xform='s/core/core-isa/' config/core.h
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--xform='s/core/core-isa/' config/core.h
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tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
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tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
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sed -n '1,/*\//p;/pc/,/a15/p' > "$TARGET"/gdb-config.c
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sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
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NUM_REGS=$(grep XTREG "$TARGET"/gdb-config.c | wc -l)
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cat <<EOF > "${TARGET}.c"
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cat <<EOF > "${TARGET}.c"
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#include "cpu.h"
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#include "cpu.h"
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@ -34,10 +33,9 @@ cat <<EOF > "${TARGET}.c"
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#include "core-$NAME/core-isa.h"
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#include "core-$NAME/core-isa.h"
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#include "overlay_tool.h"
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#include "overlay_tool.h"
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static const XtensaConfig $NAME __attribute__((unused)) = {
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static XtensaConfig $NAME __attribute__((unused)) = {
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.name = "$NAME",
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.name = "$NAME",
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.gdb_regmap = {
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.gdb_regmap = {
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.num_regs = $NUM_REGS,
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.reg = {
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.reg = {
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#include "core-$NAME/gdb-config.c"
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#include "core-$NAME/gdb-config.c"
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}
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}
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@ -27,7 +27,8 @@
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#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
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#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
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a1, a2, a3, a4, a5, a6) \
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a1, a2, a3, a4, a5, a6) \
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{ .targno = (no), .type = (typ), .group = (grp) },
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{ .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
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#define XTREG_END { .targno = -1 },
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#ifndef XCHAL_HAVE_DIV32
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#ifndef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 0
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#define XCHAL_HAVE_DIV32 0
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@ -316,6 +317,7 @@
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static XtensaConfigList node = { \
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static XtensaConfigList node = { \
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.config = &core, \
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.config = &core, \
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}; \
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}; \
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xtensa_finalize_config(&core); \
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xtensa_register_core(&node); \
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xtensa_register_core(&node); \
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}
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}
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#else
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#else
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@ -228,7 +228,7 @@ void xtensa_translate_init(void)
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
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cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUXtensaState, fregs[i]),
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offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
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fregnames[i]);
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fregnames[i]);
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}
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}
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@ -3206,8 +3206,9 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
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for (i = 0; i < 16; ++i) {
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for (i = 0; i < 16; ++i) {
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cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
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cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
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float32_val(env->fregs[i]),
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float32_val(env->fregs[i].f32[FP_F32_LOW]),
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*(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
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*(float *)(env->fregs[i].f32 + FP_F32_LOW),
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(i % 2) == 1 ? '\n' : ' ');
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}
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}
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}
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}
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}
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}
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