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hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

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Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-06-18 17:28:01 +10:00
parent df41cbd6bf
commit 3ef6434409
2 changed files with 15 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/riscv/opentitan.c
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@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 }, [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
} }
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
3, qdev_get_gpio_in(DEVICE(&s->plic), 3, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART0_RX_OVERFLOW_IRQ)); IBEX_UART0_RX_OVERFLOW_IRQ));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
create_unimplemented_device("riscv.lowrisc.ibex.gpio", create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi", create_unimplemented_device("riscv.lowrisc.ibex.spi",
@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen", create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",

5
include/hw/riscv/opentitan.h
View File

@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h" #include "hw/intc/ibex_plic.h"
#include "hw/char/ibex_uart.h" #include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h" #include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@ -35,6 +36,7 @@ struct LowRISCIbexSoCState {
RISCVHartArrayState cpus; RISCVHartArrayState cpus;
IbexPlicState plic; IbexPlicState plic;
IbexUartState uart; IbexUartState uart;
IbexTimerState timer;
MemoryRegion flash_mem; MemoryRegion flash_mem;
MemoryRegion rom; MemoryRegion rom;
@ -57,7 +59,7 @@ enum {
IBEX_DEV_SPI, IBEX_DEV_SPI,
IBEX_DEV_I2C, IBEX_DEV_I2C,
IBEX_DEV_PATTGEN, IBEX_DEV_PATTGEN,
IBEX_DEV_RV_TIMER, IBEX_DEV_TIMER,
IBEX_DEV_SENSOR_CTRL, IBEX_DEV_SENSOR_CTRL,
IBEX_DEV_OTP_CTRL, IBEX_DEV_OTP_CTRL,
IBEX_DEV_PWRMGR, IBEX_DEV_PWRMGR,
@ -82,6 +84,7 @@ enum {
}; };
enum { enum {
IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8, IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6, IBEX_UART0_RX_BREAK_ERR_IRQ = 6,