target/riscv: Add support for virtual interrupt setting
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
parent
a2e9f57d06
commit
3ef10a098b
@ -37,13 +37,36 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
|
||||
{
|
||||
target_ulong irqs;
|
||||
|
||||
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
|
||||
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
|
||||
target_ulong pending = env->mip & env->mie;
|
||||
target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
|
||||
target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
|
||||
target_ulong irqs = (pending & ~env->mideleg & -mie) |
|
||||
(pending & env->mideleg & -sie);
|
||||
target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
|
||||
|
||||
target_ulong pending = env->mip & env->mie &
|
||||
~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
|
||||
target_ulong vspending = (env->mip & env->mie &
|
||||
(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
|
||||
|
||||
target_ulong mie = env->priv < PRV_M ||
|
||||
(env->priv == PRV_M && mstatus_mie);
|
||||
target_ulong sie = env->priv < PRV_S ||
|
||||
(env->priv == PRV_S && mstatus_sie);
|
||||
target_ulong hs_sie = env->priv < PRV_S ||
|
||||
(env->priv == PRV_S && hs_mstatus_sie);
|
||||
|
||||
if (riscv_cpu_virt_enabled(env)) {
|
||||
target_ulong pending_hs_irq = pending & -hs_sie;
|
||||
|
||||
if (pending_hs_irq) {
|
||||
riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
|
||||
return ctz64(pending_hs_irq);
|
||||
}
|
||||
|
||||
pending = vspending;
|
||||
}
|
||||
|
||||
irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie);
|
||||
|
||||
if (irqs) {
|
||||
return ctz64(irqs); /* since non-zero */
|
||||
|
Loading…
Reference in New Issue
Block a user