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target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT

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We will enable more uses of this bit in the future.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2023-04-12 13:43:19 +02:00 committed by Alistair Francis
parent 0f58cbbeea
commit 3df44173e9
3 changed files with 6 additions and 4 deletions
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2
target/riscv/cpu_helper.c
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@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
return mmu_idx & MMU_HYP_ACCESS_BIT;
return mmu_idx & MMU_2STAGE_BIT;
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)

6
target/riscv/internals.h
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@ -27,13 +27,15 @@
* - S 0b001
* - S+SUM 0b010
* - M 0b011
* - HLV/HLVX/HSV adds 0b100
* - U+2STAGE 0b100
* - S+2STAGE 0b101
* - S+SUM+2STAGE 0b110
*/
#define MMUIdx_U 0
#define MMUIdx_S 1
#define MMUIdx_S_SUM 2
#define MMUIdx_M 3
#define MMU_HYP_ACCESS_BIT (1 << 2)
#define MMU_2STAGE_BIT (1 << 2)
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)

2
target/riscv/op_helper.c
View File

@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT;
return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)