cosmetics (Thiemo Seufer)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1936 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-05-22 22:13:29 +00:00
parent 42fe404458
commit 3d9fb9fefe
3 changed files with 12 additions and 15 deletions

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@ -40,8 +40,8 @@ static int map_address (CPUState *env, target_ulong *physical, int *prot,
int ret; int ret;
ret = -2; ret = -2;
tag = (address & 0xFFFFE000); tag = address & 0xFFFFE000;
ASID = env->CP0_EntryHi & 0x000000FF; ASID = env->CP0_EntryHi & 0xFF;
for (i = 0; i < MIPS_TLB_NB; i++) { for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i]; tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */ /* Check ASID, virtual page number & size */
@ -74,7 +74,7 @@ int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
int ret; int ret;
/* User mode can only access useg */ /* User mode can only access useg */
user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0; user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
#if 0 #if 0
if (logfile) { if (logfile) {
fprintf(logfile, "user mode %d h %08x\n", fprintf(logfile, "user mode %d h %08x\n",
@ -231,7 +231,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
env->CP0_Context = (env->CP0_Context & 0xff800000) | env->CP0_Context = (env->CP0_Context & 0xff800000) |
((address >> 9) & 0x007ffff0); ((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = env->CP0_EntryHi =
(env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000); (env->CP0_EntryHi & 0xFF) | (address & 0xFFFFF000);
env->exception_index = exception; env->exception_index = exception;
env->error_code = error_code; env->error_code = error_code;
ret = 1; ret = 1;

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@ -330,13 +330,13 @@ void do_mtc0 (int reg, int sel)
rn = "Index"; rn = "Index";
break; break;
case 2: case 2:
val = T0 & 0x03FFFFFFF; val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo0; old = env->CP0_EntryLo0;
env->CP0_EntryLo0 = val; env->CP0_EntryLo0 = val;
rn = "EntryLo0"; rn = "EntryLo0";
break; break;
case 3: case 3:
val = T0 & 0x03FFFFFFF; val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo1; old = env->CP0_EntryLo1;
env->CP0_EntryLo1 = val; env->CP0_EntryLo1 = val;
rn = "EntryLo1"; rn = "EntryLo1";
@ -403,20 +403,17 @@ void do_mtc0 (int reg, int sel)
old, val, env->CP0_Cause, old & mask, val & mask, old, val, env->CP0_Cause, old & mask, val & mask,
env->CP0_Cause & mask); env->CP0_Cause & mask);
} }
#if 1
if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
!(env->hflags & MIPS_HFLAG_EXL) && !(env->hflags & MIPS_HFLAG_EXL) &&
!(env->hflags & MIPS_HFLAG_ERL) && !(env->hflags & MIPS_HFLAG_ERL) &&
!(env->hflags & MIPS_HFLAG_DM) && !(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & env->CP0_Cause & mask)) { (env->CP0_Status & env->CP0_Cause & mask)) {
if (logfile) if (logfile)
fprintf(logfile, "Raise pending IRQs\n"); fprintf(logfile, "Raise pending IRQs\n");
env->interrupt_request |= CPU_INTERRUPT_HARD; env->interrupt_request |= CPU_INTERRUPT_HARD;
do_raise_exception(EXCP_EXT_INTERRUPT); } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
} else if (!(val & 0x00000001) && (old & 0x00000001)) {
env->interrupt_request &= ~CPU_INTERRUPT_HARD; env->interrupt_request &= ~CPU_INTERRUPT_HARD;
} }
#endif
rn = "Status"; rn = "Status";
break; break;
case 13: case 13:
@ -605,9 +602,9 @@ void do_tlbp (void)
uint8_t ASID; uint8_t ASID;
int i; int i;
tag = (env->CP0_EntryHi & 0xFFFFE000); tag = env->CP0_EntryHi & 0xFFFFE000;
ASID = env->CP0_EntryHi & 0x000000FF; ASID = env->CP0_EntryHi & 0xFF;
for (i = 0; i < MIPS_TLB_NB; i++) { for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i]; tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */ /* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {

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@ -1614,7 +1614,7 @@ int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
ctx.mem_idx = 0; ctx.mem_idx = 0;
#else #else
ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1; ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
#endif #endif
ctx.CP0_Status = env->CP0_Status; ctx.CP0_Status = env->CP0_Status;
#ifdef DEBUG_DISAS #ifdef DEBUG_DISAS