target/arm: Add isar_feature tests for PAN + ATS1E1
Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
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FIELD(ID_ISAR6, SB, 12, 4)
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FIELD(ID_ISAR6, SPECRES, 16, 4)
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FIELD(ID_MMFR3, CMAINTVA, 0, 4)
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FIELD(ID_MMFR3, CMAINTSW, 4, 4)
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FIELD(ID_MMFR3, BPMAINT, 8, 4)
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FIELD(ID_MMFR3, MAINTBCST, 12, 4)
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FIELD(ID_MMFR3, PAN, 16, 4)
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FIELD(ID_MMFR3, COHWALK, 20, 4)
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FIELD(ID_MMFR3, CMEMSZ, 24, 4)
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FIELD(ID_MMFR3, SUPERSEC, 28, 4)
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FIELD(ID_MMFR4, SPECSEI, 0, 4)
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FIELD(ID_MMFR4, AC2, 4, 4)
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FIELD(ID_MMFR4, XNX, 8, 4)
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@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
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return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
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}
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static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
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}
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static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
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}
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/*
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* 64-bit feature tests via id registers.
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*/
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@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
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}
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static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
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}
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static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
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}
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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