hw/timer/imx_epit: hard reset initializes CR with 0
Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -99,12 +99,14 @@ static void imx_epit_set_freq(IMXEPITState *s)
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/*
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* This is called both on hardware (device) reset and software reset.
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*/
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static void imx_epit_reset(DeviceState *dev)
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static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
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{
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IMXEPITState *s = IMX_EPIT(dev);
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/* Soft reset doesn't touch some bits; hard reset clears them */
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s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
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if (is_hard_reset) {
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s->cr = 0;
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} else {
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s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
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}
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s->sr = 0;
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s->lr = EPIT_TIMER_MAX;
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s->cmp = 0;
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@ -205,7 +207,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
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s->cr = value & 0x03ffffff;
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if (s->cr & CR_SWR) {
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/* handle the reset */
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imx_epit_reset(DEVICE(s));
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imx_epit_reset(s, false);
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}
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/*
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@ -377,12 +379,18 @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
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s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
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}
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static void imx_epit_dev_reset(DeviceState *dev)
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{
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IMXEPITState *s = IMX_EPIT(dev);
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imx_epit_reset(s, true);
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}
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static void imx_epit_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_epit_realize;
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dc->reset = imx_epit_reset;
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dc->reset = imx_epit_dev_reset;
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dc->vmsd = &vmstate_imx_timer_epit;
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dc->desc = "i.MX periodic timer";
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}
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