target-m68k: some bit ops cleanup
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -1290,39 +1290,36 @@ DISAS_INSN(bitop_reg)
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else
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opsize = OS_LONG;
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op = (insn >> 6) & 3;
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SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
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gen_flush_flags(s);
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SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
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src2 = DREG(insn, 9);
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dest = tcg_temp_new();
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tmp = tcg_temp_new();
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src2 = tcg_temp_new();
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if (opsize == OS_BYTE)
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tcg_gen_andi_i32(tmp, src2, 7);
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tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
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else
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tcg_gen_andi_i32(tmp, src2, 31);
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tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
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src2 = tcg_const_i32(1);
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tcg_gen_shl_i32(src2, src2, tmp);
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tcg_temp_free(tmp);
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tmp = tcg_const_i32(1);
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tcg_gen_shl_i32(tmp, tmp, src2);
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tcg_temp_free(src2);
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tcg_gen_and_i32(QREG_CC_Z, src1, src2);
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tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
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dest = tcg_temp_new();
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switch (op) {
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case 1: /* bchg */
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tcg_gen_xor_i32(dest, src1, src2);
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tcg_gen_xor_i32(dest, src1, tmp);
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break;
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case 2: /* bclr */
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tcg_gen_andc_i32(dest, src1, src2);
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tcg_gen_andc_i32(dest, src1, tmp);
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break;
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case 3: /* bset */
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tcg_gen_or_i32(dest, src1, src2);
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tcg_gen_or_i32(dest, src1, tmp);
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break;
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default: /* btst */
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break;
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}
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tcg_temp_free(src2);
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tcg_temp_free(tmp);
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if (op) {
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DEST_EA(env, insn, opsize, dest, &addr);
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}
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@ -1406,17 +1403,16 @@ DISAS_INSN(bitop_im)
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return;
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}
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gen_flush_flags(s);
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SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
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gen_flush_flags(s);
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if (opsize == OS_BYTE)
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bitnum &= 7;
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else
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bitnum &= 31;
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mask = 1 << bitnum;
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tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
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tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
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if (op) {
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tmp = tcg_temp_new();
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