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semihosting: Split common_semi_flen_buf per target

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We already have some larger ifdef blocks for ARM and RISCV;
split out common_semi_stack_bottom per target.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-29 13:59:52 -07:00
parent ef9c5ea85d
commit 3c820ddc1b
1 changed files with 21 additions and 23 deletions
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40
semihosting/arm-compat-semi.c
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@ -217,6 +217,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
{ {
return is_a64(env); return is_a64(env);
} }
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
#endif /* TARGET_ARM */ #endif /* TARGET_ARM */
#ifdef TARGET_RISCV #ifdef TARGET_RISCV
@ -246,6 +253,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
{ {
return riscv_cpu_mxl(env) != MXL_RV32; return riscv_cpu_mxl(env) != MXL_RV32;
} }
static inline target_ulong common_semi_stack_bottom(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
#endif #endif
/* /*
@ -301,31 +315,15 @@ static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
common_semi_set_ret(cs, ret); common_semi_set_ret(cs, ret);
} }
static target_ulong common_semi_flen_buf(CPUState *cs) /*
{ * Return an address in target memory of 64 bytes where the remote
target_ulong sp;
#ifdef TARGET_ARM
/* Return an address in target memory of 64 bytes where the remote
* gdb should write its stat struct. (The format of this structure * gdb should write its stat struct. (The format of this structure
* is defined by GDB's remote protocol and is not target-specific.) * is defined by GDB's remote protocol and is not target-specific.)
* We put this on the guest's stack just below SP. * We put this on the guest's stack just below SP.
*/ */
ARMCPU *cpu = ARM_CPU(cs); static target_ulong common_semi_flen_buf(CPUState *cs)
CPUARMState *env = &cpu->env; {
target_ulong sp = common_semi_stack_bottom(cs);
if (is_a64(env)) {
sp = env->xregs[31];
} else {
sp = env->regs[13];
}
#endif
#ifdef TARGET_RISCV
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
sp = env->gpr[xSP];
#endif
return sp - 64; return sp - 64;
} }