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Fix PPCEMB for 32bit hosts.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3059 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-07-11 10:36:47 +00:00
parent 8144219297
commit 3c4c9f9f51
2 changed files with 6 additions and 6 deletions
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2
target-ppc/cpu.h
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@ -693,7 +693,7 @@ struct CPUPPCState {
/* temporary fixed-point registers /* temporary fixed-point registers
* used to emulate 64 bits target on 32 bits hosts * used to emulate 64 bits target on 32 bits hosts
*/ */
target_ulong t0, t1, t2; ppc_gpr_t t0, t1, t2;
#endif #endif
ppc_avr_t t0_avr, t1_avr, t2_avr; ppc_avr_t t0_avr, t1_avr, t2_avr;

10
target-ppc/exec.h
View File

@ -43,15 +43,15 @@ register unsigned long T1 asm(AREG2);
register unsigned long T2 asm(AREG3); register unsigned long T2 asm(AREG3);
#endif #endif
/* We may, sometime, need 64 bits registers on 32 bits target */ /* We may, sometime, need 64 bits registers on 32 bits target */
#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64) #if TARGET_GPR_BITS > HOST_LONG_BITS
#define T0_64 T0
#define T1_64 T1
#define T2_64 T2
#else
/* no registers can be used */ /* no registers can be used */
#define T0_64 (env->t0) #define T0_64 (env->t0)
#define T1_64 (env->t1) #define T1_64 (env->t1)
#define T2_64 (env->t2) #define T2_64 (env->t2)
#else
#define T0_64 T0
#define T1_64 T1
#define T2_64 T2
#endif #endif
/* Provision for Altivec */ /* Provision for Altivec */
#define T0_avr (env->t0_avr) #define T0_avr (env->t0_avr)