linux-user: move aarch64 cpu loop to aarch64 directory
No code change, only move code from main.c to aarch64/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-4-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier
parent
3f8258c1c8
commit
3c439b1762
@ -21,6 +21,162 @@
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#include "qemu.h"
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#include "cpu_loop-common.h"
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#define get_user_code_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_code_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define get_user_data_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_data_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define put_user_data_u32(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap32(__x); \
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} \
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put_user_u32(__x, (gaddr)); \
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})
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#define put_user_data_u16(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap16(__x); \
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} \
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put_user_u16(__x, (gaddr)); \
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})
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/* AArch64 main loop */
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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int trapnr, sig;
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abi_long ret;
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target_siginfo_t info;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch (trapnr) {
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case EXCP_SWI:
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ret = do_syscall(env,
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env->xregs[8],
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env->xregs[0],
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env->xregs[1],
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env->xregs[2],
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env->xregs[3],
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env->xregs[4],
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env->xregs[5],
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0, 0);
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if (ret == -TARGET_ERESTARTSYS) {
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env->pc -= 4;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->xregs[0] = ret;
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_UDEF:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPN;
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info._sifields._sigfault._addr = env->pc;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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/* XXX: check env->error_code */
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->exception.vaddress;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_DEBUG:
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case EXCP_BKPT:
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sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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if (sig) {
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info.si_signo = sig;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP_SEMIHOST:
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env->xregs[0] = do_arm_semihosting(env);
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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process_pending_signals(env);
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/* Exception return on AArch64 always clears the exclusive monitor,
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* so any return to running guest code implies this.
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*/
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env->exclusive_addr = -1;
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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TaskState *ts = cpu->opaque;
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struct image_info *info = ts->info;
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int i;
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if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
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fprintf(stderr,
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"The selected ARM CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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for (i = 0; i < 31; i++) {
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env->xregs[i] = regs->regs[i];
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}
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env->pc = regs->pc;
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env->xregs[31] = regs->sp;
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#ifdef TARGET_WORDS_BIGENDIAN
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env->cp15.sctlr_el[1] |= SCTLR_E0E;
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for (i = 1; i < 4; ++i) {
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env->cp15.sctlr_el[i] |= SCTLR_EE;
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}
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#endif
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ts->stack_base = info->start_stack;
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ts->heap_base = info->brk;
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/* This will be filled in on the first SYS_HEAPINFO call. */
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ts->heap_limit = 0;
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}
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@ -555,89 +555,6 @@ void cpu_loop(CPUARMState *env)
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process_pending_signals(env);
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}
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}
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#else
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/* AArch64 main loop */
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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int trapnr, sig;
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abi_long ret;
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target_siginfo_t info;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch (trapnr) {
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case EXCP_SWI:
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ret = do_syscall(env,
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env->xregs[8],
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env->xregs[0],
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env->xregs[1],
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env->xregs[2],
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env->xregs[3],
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env->xregs[4],
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env->xregs[5],
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0, 0);
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if (ret == -TARGET_ERESTARTSYS) {
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env->pc -= 4;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->xregs[0] = ret;
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_UDEF:
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPN;
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info._sifields._sigfault._addr = env->pc;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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/* XXX: check env->error_code */
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->exception.vaddress;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_DEBUG:
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case EXCP_BKPT:
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sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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if (sig) {
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info.si_signo = sig;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP_SEMIHOST:
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env->xregs[0] = do_arm_semihosting(env);
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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process_pending_signals(env);
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/* Exception return on AArch64 always clears the exclusive monitor,
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* so any return to running guest code implies this.
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*/
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env->exclusive_addr = -1;
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}
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}
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#endif /* ndef TARGET_ABI32 */
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#endif
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@ -4495,29 +4412,7 @@ int main(int argc, char **argv, char **envp)
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target_cpu_copy_regs(env, regs);
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#if defined(TARGET_AARCH64)
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{
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int i;
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if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
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fprintf(stderr,
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"The selected ARM CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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for (i = 0; i < 31; i++) {
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env->xregs[i] = regs->regs[i];
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}
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env->pc = regs->pc;
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env->xregs[31] = regs->sp;
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#ifdef TARGET_WORDS_BIGENDIAN
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env->cp15.sctlr_el[1] |= SCTLR_E0E;
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for (i = 1; i < 4; ++i) {
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env->cp15.sctlr_el[i] |= SCTLR_EE;
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}
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#endif
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}
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#elif defined(TARGET_ARM)
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#if defined(TARGET_ARM) && !defined(TARGET_AARCH64)
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{
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int i;
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cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
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@ -4772,7 +4667,7 @@ int main(int argc, char **argv, char **envp)
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}
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#endif
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#if defined(TARGET_ARM) || defined(TARGET_M68K)
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#if (defined(TARGET_ARM) && !defined(TARGET_AARCH64)) || defined(TARGET_M68K)
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ts->stack_base = info->start_stack;
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ts->heap_base = info->brk;
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/* This will be filled in on the first SYS_HEAPINFO call. */
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