linux-user/hppa: Force all code addresses to PRIV_USER
The kernel does this along the return path to user mode. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1887,8 +1887,8 @@ static inline void init_thread(struct target_pt_regs *regs,
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static inline void init_thread(struct target_pt_regs *regs,
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struct image_info *infop)
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{
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regs->iaoq[0] = infop->entry;
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regs->iaoq[1] = infop->entry + 4;
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regs->iaoq[0] = infop->entry | PRIV_USER;
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regs->iaoq[1] = regs->iaoq[0] + 4;
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regs->gr[23] = 0;
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regs->gr[24] = infop->argv;
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regs->gr[25] = infop->argc;
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@ -129,8 +129,8 @@ void cpu_loop(CPUHPPAState *env)
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default:
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env->gr[28] = ret;
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/* We arrived here by faking the gateway page. Return. */
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env->iaoq_f = env->gr[31];
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env->iaoq_b = env->gr[31] + 4;
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env->iaoq_f = env->gr[31] | PRIV_USER;
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env->iaoq_b = env->iaoq_f + 4;
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break;
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case -QEMU_ERESTARTSYS:
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case -QEMU_ESIGRETURN:
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@ -140,8 +140,8 @@ void cpu_loop(CPUHPPAState *env)
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case EXCP_SYSCALL_LWS:
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env->gr[21] = hppa_lws(env);
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/* We arrived here by faking the gateway page. Return. */
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env->iaoq_f = env->gr[31];
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env->iaoq_b = env->gr[31] + 4;
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env->iaoq_f = env->gr[31] | PRIV_USER;
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env->iaoq_b = env->iaoq_f + 4;
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break;
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case EXCP_IMP:
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force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f);
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@ -152,9 +152,9 @@ void cpu_loop(CPUHPPAState *env)
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case EXCP_PRIV_OPR:
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/* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */
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if (env->cr[CR_IIR] == 0x04000000) {
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
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} else {
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f);
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f);
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}
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break;
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case EXCP_PRIV_REG:
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@ -170,7 +170,7 @@ void cpu_loop(CPUHPPAState *env)
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force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f);
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break;
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case EXCP_BREAK:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3);
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f);
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break;
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case EXCP_DEBUG:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f);
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@ -101,7 +101,9 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc)
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cpu_hppa_loaded_fr0(env);
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__get_user(env->iaoq_f, &sc->sc_iaoq[0]);
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env->iaoq_f |= PRIV_USER;
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__get_user(env->iaoq_b, &sc->sc_iaoq[1]);
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env->iaoq_b |= PRIV_USER;
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__get_user(env->cr[CR_SAR], &sc->sc_sar);
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}
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@ -162,8 +164,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
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unlock_user(fdesc, haddr, 0);
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haddr = dest;
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}
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env->iaoq_f = haddr;
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env->iaoq_b = haddr + 4;
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env->iaoq_f = haddr | PRIV_USER;
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env->iaoq_b = env->iaoq_f + 4;
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env->psw_n = 0;
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return;
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@ -28,8 +28,8 @@ static inline void cpu_clone_regs_child(CPUHPPAState *env, target_ulong newsp,
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/* Indicate child in return value. */
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env->gr[28] = 0;
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/* Return from the syscall. */
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env->iaoq_f = env->gr[31];
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env->iaoq_b = env->gr[31] + 4;
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env->iaoq_f = env->gr[31] | PRIV_USER;
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env->iaoq_b = env->iaoq_f + 4;
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}
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static inline void cpu_clone_regs_parent(CPUHPPAState *env, unsigned flags)
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@ -32,6 +32,9 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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#ifdef CONFIG_USER_ONLY
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value |= PRIV_USER;
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#endif
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cpu->env.iaoq_f = value;
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cpu->env.iaoq_b = value + 4;
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}
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@ -93,8 +96,8 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
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tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
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#ifdef CONFIG_USER_ONLY
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cpu->env.iaoq_f = tb->pc;
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cpu->env.iaoq_b = tb->cs_base;
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cpu->env.iaoq_f = tb->pc | PRIV_USER;
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cpu->env.iaoq_b = tb->cs_base | PRIV_USER;
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#else
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/* Recover the IAOQ values from the GVA + PRIV. */
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uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
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@ -42,6 +42,9 @@
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#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
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#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
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#define PRIV_KERNEL 0
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#define PRIV_USER 3
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#define TARGET_INSN_START_EXTRA_WORDS 2
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/* No need to flush MMU_ABS*_IDX */
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@ -163,12 +163,18 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31);
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break;
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case 33:
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#ifdef CONFIG_USER_ONLY
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val |= PRIV_USER;
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#endif
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env->iaoq_f = val;
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break;
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case 34:
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env->iasq_f = (uint64_t)val << 32;
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break;
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case 35:
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#ifdef CONFIG_USER_ONLY
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val |= PRIV_USER;
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#endif
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env->iaoq_b = val;
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break;
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case 36:
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@ -2054,7 +2054,7 @@ static void do_page_zero(DisasContext *ctx)
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tcg_gen_st_i64(cpu_gr[26], tcg_env,
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offsetof(CPUHPPAState, cr[27]));
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tcg_gen_ori_i64(next.base, cpu_gr[31], 3);
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tcg_gen_ori_i64(next.base, cpu_gr[31], PRIV_USER);
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install_iaq_entries(ctx, &next, NULL);
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ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
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}
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@ -4583,7 +4583,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->is_pa20 = hppa_is_pa20(cpu_env(cs));
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#ifdef CONFIG_USER_ONLY
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ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);
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ctx->privilege = PRIV_USER;
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ctx->mmu_idx = MMU_USER_IDX;
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ctx->iaoq_first = ctx->base.pc_first | ctx->privilege;
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ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first;
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