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hw/riscv: Allow creating multiple instances of CLINT

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We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2020-05-14 15:51:31 +05:30 committed by Alistair Francis
parent 7774e403f2
commit 3bf03f0899
6 changed files with 20 additions and 15 deletions
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20
hw/riscv/sifive_clint.c
View File

@ -79,7 +79,7 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
SiFiveCLINTState *clint = opaque; SiFiveCLINTState *clint = opaque;
if (addr >= clint->sip_base && if (addr >= clint->sip_base &&
addr < clint->sip_base + (clint->num_harts << 2)) { addr < clint->sip_base + (clint->num_harts << 2)) {
size_t hartid = (addr - clint->sip_base) >> 2; size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
CPUState *cpu = qemu_get_cpu(hartid); CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL; CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) { if (!env) {
@ -92,7 +92,8 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
} }
} else if (addr >= clint->timecmp_base && } else if (addr >= clint->timecmp_base &&
addr < clint->timecmp_base + (clint->num_harts << 3)) { addr < clint->timecmp_base + (clint->num_harts << 3)) {
size_t hartid = (addr - clint->timecmp_base) >> 3; size_t hartid = clint->hartid_base +
((addr - clint->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid); CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL; CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) { if (!env) {
@ -129,7 +130,7 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
if (addr >= clint->sip_base && if (addr >= clint->sip_base &&
addr < clint->sip_base + (clint->num_harts << 2)) { addr < clint->sip_base + (clint->num_harts << 2)) {
size_t hartid = (addr - clint->sip_base) >> 2; size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
CPUState *cpu = qemu_get_cpu(hartid); CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL; CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) { if (!env) {
@ -142,7 +143,8 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
return; return;
} else if (addr >= clint->timecmp_base && } else if (addr >= clint->timecmp_base &&
addr < clint->timecmp_base + (clint->num_harts << 3)) { addr < clint->timecmp_base + (clint->num_harts << 3)) {
size_t hartid = (addr - clint->timecmp_base) >> 3; size_t hartid = clint->hartid_base +
((addr - clint->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid); CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL; CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) { if (!env) {
@ -186,6 +188,7 @@ static const MemoryRegionOps sifive_clint_ops = {
}; };
static Property sifive_clint_properties[] = { static Property sifive_clint_properties[] = {
DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0),
DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0), DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0), DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
@ -227,13 +230,13 @@ type_init(sifive_clint_register_types)
/* /*
* Create CLINT device. * Create CLINT device.
*/ */
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
bool provide_rdtime) uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
{ {
int i; int i;
for (i = 0; i < num_harts; i++) { for (i = 0; i < num_harts; i++) {
CPUState *cpu = qemu_get_cpu(i); CPUState *cpu = qemu_get_cpu(hartid_base + i);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL; CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) { if (!env) {
continue; continue;
@ -247,6 +250,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
} }
DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT); DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "num-harts", num_harts);
qdev_prop_set_uint32(dev, "sip-base", sip_base); qdev_prop_set_uint32(dev, "sip-base", sip_base);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);

2
hw/riscv/sifive_e.c
View File

@ -211,7 +211,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_CONTEXT_STRIDE, SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_PLIC].size); memmap[SIFIVE_E_PLIC].size);
sifive_clint_create(memmap[SIFIVE_E_CLINT].base, sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
create_unimplemented_device("riscv.sifive.e.aon", create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);

2
hw/riscv/sifive_u.c
View File

@ -703,7 +703,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base, sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {

2
hw/riscv/spike.c
View File

@ -234,7 +234,7 @@ static void spike_board_init(MachineState *machine)
/* Core Local Interruptor (timer and IPI) */ /* Core Local Interruptor (timer and IPI) */
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
false); false);
} }

2
hw/riscv/virt.c
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@ -571,7 +571,7 @@ static void virt_machine_init(MachineState *machine)
VIRT_PLIC_CONTEXT_STRIDE, VIRT_PLIC_CONTEXT_STRIDE,
memmap[VIRT_PLIC].size); memmap[VIRT_PLIC].size);
sifive_clint_create(memmap[VIRT_CLINT].base, sifive_clint_create(memmap[VIRT_CLINT].base,
memmap[VIRT_CLINT].size, smp_cpus, memmap[VIRT_CLINT].size, 0, smp_cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
sifive_test_create(memmap[VIRT_TEST].base); sifive_test_create(memmap[VIRT_TEST].base);

7
include/hw/riscv/sifive_clint.h
View File

@ -33,6 +33,7 @@ typedef struct SiFiveCLINTState {
/*< public >*/ /*< public >*/
MemoryRegion mmio; MemoryRegion mmio;
uint32_t hartid_base;
uint32_t num_harts; uint32_t num_harts;
uint32_t sip_base; uint32_t sip_base;
uint32_t timecmp_base; uint32_t timecmp_base;
@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState {
uint32_t aperture_size; uint32_t aperture_size;
} SiFiveCLINTState; } SiFiveCLINTState;
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
bool provide_rdtime); uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
enum { enum {
SIFIVE_SIP_BASE = 0x0, SIFIVE_SIP_BASE = 0x0,