MIPS patches queue
- Remove -Wclobbered in nanoMIPS disassembler (Richard Henderson) - Fix invalid string formats in nanoMIPS disassembler (myself) - Allow Loongson-2F to access XKPHYS in kernel mode (Jiaxun Yang) - Octeon opcode fixes (Jiaxun Yang, Pavel Dovgalyuk) - MAINTAINERS nanoMIPS update -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmNpnTYACgkQ4+MsLN6t wN4t2A//XLIH7uL+u6kqGm45fVyy58R1NDoj2afNv5rRqIcXSrP9zRH00woLmGzs pYLbu3yOynY2/OSU3iooAaXjQz8ub3YIpceAQdD26OgnpTrwVzKO9jvQz2UlDrzs gETnHfqwZDBzxbqkUXxT7Pe3NRQzRmMgrMYNJm+e7UokCVy3c2PZ6vBdC5zvwS6K LwnuEBvG74fV70D42dYay0wTB37z7m5Cf7uMp7TrEA+2HLgIZl+J9AuCmZxZZxdU sh0AvNiVaKbHT55lazWAMvmVuUEl5zLTEUa1B0sOv081ZaY3ACBuh6Q8VpNgkgSx qxKQbye+LtnDDYckeIRa3jI5Fs5AagC6lPPJJpiiFnMqpQaPYhNDFFjR5LNdwfQ6 cN1lU4toi2B5LuUmiCEJrAsMgocLaNVnhwas391vtIFZh+onN/wZ1sE1Ur1kZkL7 and2QDr2C8Y7qnpP3q8QRSz1yz+pyvTRcRIwjrnRGIgOfQUOiYeLB1RO01VOFn8u 0Oa5gKrtClnQxMfZqoRIGucrnbZdrP/oHwsVOKUdDDNpAceVEJ0dvBiUv6WhQQ/4 G6Ih2GJ/gJU3Ld8UliA9MCzISbvNoQ6EHYk0YqrH8B/MCzvOLbbmaZban3+xFTma c2YGQ16ZIQsZMm00sB1Du8l9H9ms/N0VJcSx9txD2YbQWOA/bMs= =gQ7f -----END PGP SIGNATURE----- Merge tag 'mips-20221108' of https://github.com/philmd/qemu into staging MIPS patches queue - Remove -Wclobbered in nanoMIPS disassembler (Richard Henderson) - Fix invalid string formats in nanoMIPS disassembler (myself) - Allow Loongson-2F to access XKPHYS in kernel mode (Jiaxun Yang) - Octeon opcode fixes (Jiaxun Yang, Pavel Dovgalyuk) - MAINTAINERS nanoMIPS update # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmNpnTYACgkQ4+MsLN6t # wN4t2A//XLIH7uL+u6kqGm45fVyy58R1NDoj2afNv5rRqIcXSrP9zRH00woLmGzs # pYLbu3yOynY2/OSU3iooAaXjQz8ub3YIpceAQdD26OgnpTrwVzKO9jvQz2UlDrzs # gETnHfqwZDBzxbqkUXxT7Pe3NRQzRmMgrMYNJm+e7UokCVy3c2PZ6vBdC5zvwS6K # LwnuEBvG74fV70D42dYay0wTB37z7m5Cf7uMp7TrEA+2HLgIZl+J9AuCmZxZZxdU # sh0AvNiVaKbHT55lazWAMvmVuUEl5zLTEUa1B0sOv081ZaY3ACBuh6Q8VpNgkgSx # qxKQbye+LtnDDYckeIRa3jI5Fs5AagC6lPPJJpiiFnMqpQaPYhNDFFjR5LNdwfQ6 # cN1lU4toi2B5LuUmiCEJrAsMgocLaNVnhwas391vtIFZh+onN/wZ1sE1Ur1kZkL7 # and2QDr2C8Y7qnpP3q8QRSz1yz+pyvTRcRIwjrnRGIgOfQUOiYeLB1RO01VOFn8u # 0Oa5gKrtClnQxMfZqoRIGucrnbZdrP/oHwsVOKUdDDNpAceVEJ0dvBiUv6WhQQ/4 # G6Ih2GJ/gJU3Ld8UliA9MCzISbvNoQ6EHYk0YqrH8B/MCzvOLbbmaZban3+xFTma # c2YGQ16ZIQsZMm00sB1Du8l9H9ms/N0VJcSx9txD2YbQWOA/bMs= # =gQ7f # -----END PGP SIGNATURE----- # gpg: Signature made Mon 07 Nov 2022 19:05:10 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20221108' of https://github.com/philmd/qemu: MAINTAINERS: Inherit from nanoMIPS disas/nanomips: Tidy read for 48-bit opcodes disas/nanomips: Split out read_u16 disas/nanomips: Merge insn{1,2,3} into words[3] disas/nanomips: Move setjmp into nanomips_dis disas/nanomips: Remove headers already included by "qemu/osdep.h" disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats disas/nanomips: Fix invalid PRIx64 format calling img_format() disas/nanomips: Fix invalid PRId64 format calling img_format() target/mips: Don't check COP1X for 64 bit FP mode target/mips: Disable DSP ASE for Octeon68XX target/mips: Enable LBX/LWX/* instructions for Octeon target/mips: Cast offset field of Octeon BBIT to int16_t target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
3ba5fe46ea
@ -237,16 +237,10 @@ R: Jiaxun Yang <jiaxun.yang@flygoat.com>
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R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
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S: Odd Fixes
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F: target/mips/
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F: disas/mips.c
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F: disas/*mips.c
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F: docs/system/cpu-models-mips.rst.inc
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F: tests/tcg/mips/
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MIPS TCG CPUs (nanoMIPS ISA)
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M: Stefan Pejic <stefan.pejic@syrmia.com>
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S: Maintained
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F: disas/nanomips.*
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F: target/mips/tcg/*nanomips*
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NiosII TCG CPUs
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M: Chris Wulff <crwulff@gmail.com>
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M: Marek Vasut <marex@denx.de>
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154
disas/nanomips.c
154
disas/nanomips.c
@ -30,10 +30,6 @@
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#include "qemu/osdep.h"
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#include "disas/dis-asm.h"
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#include <string.h>
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#include <stdio.h>
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#include <stdarg.h>
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typedef int64_t int64;
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typedef uint64_t uint64;
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typedef uint32_t uint32;
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@ -95,7 +91,7 @@ typedef struct Pool {
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#define IMGASSERTONCE(test)
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static char *img_format(const char *format, ...)
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static char * G_GNUC_PRINTF(1, 2) img_format(const char *format, ...)
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{
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char *buffer;
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va_list args;
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@ -3252,7 +3248,8 @@ static char *CACHE(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
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return img_format("CACHE 0x%" PRIx64 ", %" PRId64 "(%s)",
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op_value, s_value, rs);
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}
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@ -3274,7 +3271,8 @@ static char *CACHEE(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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return img_format("CACHEE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
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return img_format("CACHEE 0x%" PRIx64 ", %" PRId64 "(%s)",
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op_value, s_value, rs);
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}
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@ -5173,7 +5171,7 @@ static char *DADDIU_48_(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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return img_format("DADDIU %s, %s", rt, s_value);
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return img_format("DADDIU %s, %" PRId64, rt, s_value);
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}
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@ -11859,7 +11857,7 @@ static char *PREF_S9_(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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return img_format("PREF 0x%" PRIx64 ", %s(%s)",
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return img_format("PREF 0x%" PRIx64 ", %" PRId64 "(%s)",
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hint_value, s_value, rs);
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}
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@ -11905,7 +11903,8 @@ static char *PREFE(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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return img_format("PREFE 0x%" PRIx64 ", %s(%s)", hint_value, s_value, rs);
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return img_format("PREFE 0x%" PRIx64 ", %" PRId64 "(%s)",
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hint_value, s_value, rs);
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}
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@ -12079,7 +12078,7 @@ static char *REPL_PH(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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return img_format("REPL.PH %s, %s", rt, s_value);
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return img_format("REPL.PH %s, %" PRId64, rt, s_value);
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}
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@ -12232,7 +12231,8 @@ static char *RESTOREF(uint64 instruction, Dis_info *info)
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uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
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return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value);
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return img_format("RESTOREF 0x%" PRIx64 ", 0x%" PRIx64,
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u_value, count_value);
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}
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@ -12613,7 +12613,7 @@ static char *SB_S9_(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SB %s, %s(%s)", rt, s_value, rs);
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return img_format("SB %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12659,7 +12659,7 @@ static char *SBE(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SBE %s, %s(%s)", rt, s_value, rs);
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return img_format("SBE %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12706,7 +12706,7 @@ static char *SC(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SC %s, %s(%s)", rt, s_value, rs);
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return img_format("SC %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12729,7 +12729,7 @@ static char *SCD(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SCD %s, %s(%s)", rt, s_value, rs);
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return img_format("SCD %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12776,7 +12776,7 @@ static char *SCE(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SCE %s, %s(%s)", rt, s_value, rs);
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return img_format("SCE %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12868,7 +12868,7 @@ static char *SD_S9_(uint64 instruction, Dis_info *info)
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const char *rt = GPR(rt_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SD %s, %s(%s)", rt, s_value, rs);
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return img_format("SD %s, %" PRId64 "(%s)", rt, s_value, rs);
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}
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@ -12973,7 +12973,7 @@ static char *SDC1_S9_(uint64 instruction, Dis_info *info)
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const char *ft = FPR(ft_value, info);
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const char *rs = GPR(rs_value, info);
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return img_format("SDC1 %s, %s(%s)", ft, s_value, rs);
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return img_format("SDC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
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}
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@ -13066,7 +13066,8 @@ static char *SDC2(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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return img_format("SDC2 CP%" PRIu64 ", %s(%s)", cs_value, s_value, rs);
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return img_format("SDC2 CP%" PRIu64 ", %" PRId64 "(%s)",
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cs_value, s_value, rs);
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}
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@ -13091,7 +13092,8 @@ static char *SDM(uint64 instruction, Dis_info *info)
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const char *rs = GPR(rs_value, info);
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uint64 count3 = encode_count3_from_count(count3_value);
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return img_format("SDM %s, %s(%s), 0x%" PRIx64, rt, s_value, rs, count3);
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return img_format("SDM %s, %" PRId64 "(%s), 0x%" PRIx64,
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rt, s_value, rs, count3);
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}
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@ -21905,24 +21907,36 @@ static const Pool MAJOR[2] = {
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0x0 }, /* P16 */
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};
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static int nanomips_dis(char **buf,
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Dis_info *info,
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unsigned short one,
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unsigned short two,
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unsigned short three)
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static bool nanomips_dis(const uint16_t *data, char **buf, Dis_info *info)
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{
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uint16 bits[3] = {one, two, three};
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TABLE_ENTRY_TYPE type;
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int size = Disassemble(bits, buf, &type, MAJOR, 2, info);
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return size;
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/* Handle runtime errors. */
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if (unlikely(sigsetjmp(info->buf, 0) != 0)) {
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return false;
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}
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return Disassemble(data, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0;
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}
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static bool read_u16(uint16_t *ret, bfd_vma memaddr,
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struct disassemble_info *info)
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{
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int status = (*info->read_memory_func)(memaddr, (bfd_byte *)ret, 2, info);
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if (status != 0) {
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(*info->memory_error_func)(status, memaddr, info);
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return false;
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}
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if ((info->endian == BFD_ENDIAN_BIG) != HOST_BIG_ENDIAN) {
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bswap16s(ret);
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}
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return true;
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}
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int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
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{
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int status;
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bfd_byte buffer[2];
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uint16_t insn1 = 0, insn2 = 0, insn3 = 0;
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int length;
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uint16_t words[3] = { };
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g_autofree char *buf = NULL;
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info->bytes_per_chunk = 2;
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@ -21939,70 +21953,38 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
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disassm_info.fprintf_func = info->fprintf_func;
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disassm_info.stream = info->stream;
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status = (*info->read_memory_func)(memaddr, buffer, 2, info);
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if (status != 0) {
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(*info->memory_error_func)(status, memaddr, info);
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if (!read_u16(&words[0], memaddr, info)) {
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return -1;
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}
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if (info->endian == BFD_ENDIAN_BIG) {
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insn1 = bfd_getb16(buffer);
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} else {
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insn1 = bfd_getl16(buffer);
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}
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(*info->fprintf_func)(info->stream, "%04x ", insn1);
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length = 2;
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/* Handle 32-bit opcodes. */
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if ((insn1 & 0x1000) == 0) {
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status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);
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if (status != 0) {
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(*info->memory_error_func)(status, memaddr + 2, info);
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if ((words[0] & 0x1000) == 0) {
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if (!read_u16(&words[1], memaddr + 2, info)) {
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return -1;
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}
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length = 4;
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if (info->endian == BFD_ENDIAN_BIG) {
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insn2 = bfd_getb16(buffer);
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/* Handle 48-bit opcodes. */
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if ((words[0] >> 10) == 0x18) {
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if (!read_u16(&words[1], memaddr + 4, info)) {
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return -1;
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}
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length = 6;
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}
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}
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for (int i = 0; i < ARRAY_SIZE(words); i++) {
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if (i * 2 < length) {
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(*info->fprintf_func)(info->stream, "%04x ", words[i]);
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} else {
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insn2 = bfd_getl16(buffer);
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(*info->fprintf_func)(info->stream, " ");
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}
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(*info->fprintf_func)(info->stream, "%04x ", insn2);
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} else {
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(*info->fprintf_func)(info->stream, " ");
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}
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/* Handle 48-bit opcodes. */
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if ((insn1 >> 10) == 0x18) {
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status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);
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if (status != 0) {
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(*info->memory_error_func)(status, memaddr + 4, info);
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return -1;
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}
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if (info->endian == BFD_ENDIAN_BIG) {
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insn3 = bfd_getb16(buffer);
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} else {
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insn3 = bfd_getl16(buffer);
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}
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(*info->fprintf_func)(info->stream, "%04x ", insn3);
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} else {
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(*info->fprintf_func)(info->stream, " ");
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}
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/* Handle runtime errors. */
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if (sigsetjmp(disassm_info.buf, 0) != 0) {
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info->insn_type = dis_noninsn;
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return insn3 ? 6 : insn2 ? 4 : 2;
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if (nanomips_dis(words, &buf, &disassm_info)) {
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(*info->fprintf_func) (info->stream, "%s", buf);
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}
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int length = nanomips_dis(&buf, &disassm_info, insn1, insn2, insn3);
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/* FIXME: Should probably use a hash table on the major opcode here. */
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(*info->fprintf_func) (info->stream, "%s", buf);
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if (length > 0) {
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return length / 8;
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}
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info->insn_type = dis_noninsn;
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return insn3 ? 6 : insn2 ? 4 : 2;
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return length;
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}
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@ -934,7 +934,7 @@ const mips_def_t mips_defs[] =
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(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
|
||||
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
||||
.CP0_Config2 = MIPS_CONFIG2,
|
||||
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
|
||||
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
||||
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
|
||||
(0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
|
||||
(3U << CP0C4_MMUSizeExt),
|
||||
@ -946,7 +946,7 @@ const mips_def_t mips_defs[] =
|
||||
.CP0_Status_rw_bitmask = 0x12F8FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 49,
|
||||
.insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
|
||||
.insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
|
||||
.mmu_type = MMU_TYPE_R4000,
|
||||
},
|
||||
|
||||
|
||||
@ -302,6 +302,12 @@ static void mips_cpu_reset(DeviceState *dev)
|
||||
env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
|
||||
0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
|
||||
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
|
||||
if (env->insn_flags & INSN_LOONGSON2F) {
|
||||
/* Loongson-2F has those bits hardcoded to 1 */
|
||||
env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) |
|
||||
(1 << CP0St_UX);
|
||||
}
|
||||
|
||||
/*
|
||||
* Vectored interrupts not implemented, timer on int 7,
|
||||
* no performance counters.
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
# BBIT132 111110 ..... ..... ................
|
||||
|
||||
%bbit_p 28:1 16:5
|
||||
BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
|
||||
BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p
|
||||
|
||||
# Arithmetic
|
||||
# BADDU rd, rs, rt
|
||||
|
||||
@ -1545,7 +1545,7 @@ void check_cop1x(DisasContext *ctx)
|
||||
*/
|
||||
void check_cp1_64bitmode(DisasContext *ctx)
|
||||
{
|
||||
if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
|
||||
if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) {
|
||||
gen_reserved_instruction(ctx);
|
||||
}
|
||||
}
|
||||
@ -12173,12 +12173,16 @@ enum {
|
||||
#include "nanomips_translate.c.inc"
|
||||
|
||||
/* MIPSDSP functions. */
|
||||
static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
|
||||
int rd, int base, int offset)
|
||||
|
||||
/* Indexed load is not for DSP only */
|
||||
static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
|
||||
int rd, int base, int offset)
|
||||
{
|
||||
TCGv t0;
|
||||
|
||||
check_dsp(ctx);
|
||||
if (!(ctx->insn_flags & INSN_OCTEON)) {
|
||||
check_dsp(ctx);
|
||||
}
|
||||
t0 = tcg_temp_new();
|
||||
|
||||
if (base == 0) {
|
||||
@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
|
||||
case OPC_LBUX:
|
||||
case OPC_LHX:
|
||||
case OPC_LWX:
|
||||
gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
|
||||
gen_mips_lx(ctx, op2, rd, rs, rt);
|
||||
break;
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("MASK LX");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user