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PPC: Introduce the Virtual Time Base (VTB) SPR register

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This patch adds basic support for the VTB.

PowerISA:
The Virtual Time Base (VTB) is a 64-bit incrementing counter.
Virtual Time Base increments at the same rate as the Time Base until its value
becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value
becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when
this occurs.

The operation of the Virtual Time Base has the following additional
properties.
1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of
the Virtual Time Base.
2. Copying the contents of a GPR to the Virtual Time Base replaces the
contents of the Virtual Time Base with the contents of the GPR.

Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Cyril Bur 2015-03-02 17:55:38 +11:00 committed by Alexander Graf
parent 6494ad9bf4
commit 3ba55e399f
2 changed files with 11 additions and 0 deletions
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1
target-ppc/cpu.h
View File

@ -1624,6 +1624,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_DBRAM1 (0x32A)
#define SPR_RCPU_L2U_RA3 (0x32B)
#define SPR_TAR (0x32F)
#define SPR_VTB (0x351)
#define SPR_440_INV0 (0x370)
#define SPR_440_INV1 (0x371)
#define SPR_440_INV2 (0x372)

10
target-ppc/translate_init.c
View File

@ -7819,6 +7819,15 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
KVM_REG_PPC_BESCR, 0x00000000);
}
/* Virtual Time Base */
static void gen_spr_vtb(CPUPPCState *env)
{
spr_register(env, SPR_VTB, "VTB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
}
static void gen_spr_power8_fscr(CPUPPCState *env)
{
#if defined(CONFIG_USER_ONLY)
@ -7881,6 +7890,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_pmu_sup(env);
gen_spr_power8_pmu_user(env);
gen_spr_power8_tm(env);
gen_spr_vtb(env);
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);