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fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

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In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-04-20 09:31:48 +08:00 committed by Alistair Francis
parent d11e316d84
commit 3a7f7757ba
1 changed files with 6 additions and 0 deletions
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6
fpu/softfloat-specialize.c.inc
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@ -627,6 +627,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
} else { } else {
return 1; return 1;
} }
#elif defined(TARGET_RISCV)
/* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
if (infzero) {
float_raise(float_flag_invalid, status);
}
return 3; /* default NaN */
#elif defined(TARGET_XTENSA) #elif defined(TARGET_XTENSA)
/* /*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns