target-arm: A64: Add 2-reg-misc REV* instructions
Add the byte-reverse operations REV64, REV32 and REV16 from the two-reg-misc group. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -7446,6 +7446,75 @@ static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
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static void handle_rev(DisasContext *s, int opcode, bool u,
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bool is_q, int size, int rn, int rd)
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{
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int op = (opcode << 1) | u;
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int opsz = op + size;
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int grp_size = 3 - opsz;
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int dsize = is_q ? 128 : 64;
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int i;
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if (opsz >= 3) {
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unallocated_encoding(s);
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return;
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}
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if (size == 0) {
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/* Special case bytes, use bswap op on each group of elements */
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int groups = dsize / (8 << grp_size);
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for (i = 0; i < groups; i++) {
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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read_vec_element(s, tcg_tmp, rn, i, grp_size);
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switch (grp_size) {
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case MO_16:
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tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
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break;
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case MO_32:
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tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
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break;
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case MO_64:
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tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
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break;
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default:
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g_assert_not_reached();
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}
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write_vec_element(s, tcg_tmp, rd, i, grp_size);
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tcg_temp_free_i64(tcg_tmp);
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}
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if (!is_q) {
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clear_vec_high(s, rd);
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}
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} else {
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int revmask = (1 << grp_size) - 1;
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int esize = 8 << size;
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int elements = dsize / esize;
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TCGv_i64 tcg_rn = tcg_temp_new_i64();
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TCGv_i64 tcg_rd = tcg_const_i64(0);
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TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
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for (i = 0; i < elements; i++) {
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int e_rev = (i & 0xf) ^ revmask;
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int off = e_rev * esize;
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read_vec_element(s, tcg_rn, rn, i, size);
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if (off >= 64) {
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tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
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tcg_rn, off - 64, esize);
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} else {
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tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
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}
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}
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write_vec_element(s, tcg_rd, rd, 0, MO_64);
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write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
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tcg_temp_free_i64(tcg_rd_hi);
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tcg_temp_free_i64(tcg_rd);
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tcg_temp_free_i64(tcg_rn);
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}
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}
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/* C3.6.17 AdvSIMD two reg misc
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/* C3.6.17 AdvSIMD two reg misc
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+-----------+--------+-----+------+------+
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* +---+---+---+-----------+------+-----------+--------+-----+------+------+
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@ -7464,7 +7533,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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switch (opcode) {
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switch (opcode) {
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case 0x0: /* REV64, REV32 */
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case 0x0: /* REV64, REV32 */
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case 0x1: /* REV16 */
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case 0x1: /* REV16 */
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unsupported_encoding(s, insn);
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handle_rev(s, opcode, u, is_q, size, rn, rd);
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return;
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return;
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case 0x5: /* CNT, NOT, RBIT */
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case 0x5: /* CNT, NOT, RBIT */
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if (u && size == 0) {
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if (u && size == 0) {
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