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target/riscv/csr.c: use 'vlenb' instead of 'vlen'

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As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240122161107.26737-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-01-22 13:10:56 -03:00 committed by Alistair Francis
parent 04eb30a03c
commit 39b5efa5b8
1 changed files with 2 additions and 2 deletions
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4
target/riscv/csr.c
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@ -683,7 +683,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = riscv_cpu_cfg(env)->vlen >> 3; *val = riscv_cpu_cfg(env)->vlenb;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -738,7 +738,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
* The vstart CSR is defined to have only enough writable bits * The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits. * to hold the largest element index, i.e. lg2(VLEN) bits.
*/ */
env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen)); env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3));
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }