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arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE

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Now no users are setting the frq properties on the CMSDK timer,
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
properties and the struct fields that back them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210128114145.20536-25-peter.maydell@linaro.org
Message-id: 20210121190622.22000-25-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-01-28 11:41:44 +00:00
parent 911612989d
commit 38867d0b7e
8 changed files with 0 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/arm/armsse.c
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@ -48,7 +48,6 @@ static Property iotkit_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *), MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
@ -60,7 +59,6 @@ static Property armsse_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *), MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),

6
hw/timer/cmsdk-apb-dualtimer.c
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@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
} }
}; };
static Property cmsdk_apb_dualtimer_properties[] = {
DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_dualtimer_realize; dc->realize = cmsdk_apb_dualtimer_realize;
dc->vmsd = &cmsdk_apb_dualtimer_vmstate; dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
dc->reset = cmsdk_apb_dualtimer_reset; dc->reset = cmsdk_apb_dualtimer_reset;
device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
} }
static const TypeInfo cmsdk_apb_dualtimer_info = { static const TypeInfo cmsdk_apb_dualtimer_info = {

6
hw/timer/cmsdk-apb-timer.c
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@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
} }
}; };
static Property cmsdk_apb_timer_properties[] = {
DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_timer_realize; dc->realize = cmsdk_apb_timer_realize;
dc->vmsd = &cmsdk_apb_timer_vmstate; dc->vmsd = &cmsdk_apb_timer_vmstate;
dc->reset = cmsdk_apb_timer_reset; dc->reset = cmsdk_apb_timer_reset;
device_class_set_props(dc, cmsdk_apb_timer_properties);
} }
static const TypeInfo cmsdk_apb_timer_info = { static const TypeInfo cmsdk_apb_timer_info = {

6
hw/watchdog/cmsdk-apb-watchdog.c
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@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
} }
}; };
static Property cmsdk_apb_watchdog_properties[] = {
DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_watchdog_realize; dc->realize = cmsdk_apb_watchdog_realize;
dc->vmsd = &cmsdk_apb_watchdog_vmstate; dc->vmsd = &cmsdk_apb_watchdog_vmstate;
dc->reset = cmsdk_apb_watchdog_reset; dc->reset = cmsdk_apb_watchdog_reset;
device_class_set_props(dc, cmsdk_apb_watchdog_properties);
} }
static const TypeInfo cmsdk_apb_watchdog_info = { static const TypeInfo cmsdk_apb_watchdog_info = {

2
include/hw/arm/armsse.h
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@ -41,7 +41,6 @@
* + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
* + QOM property "memory" is a MemoryRegion containing the devices provided * + QOM property "memory" is a MemoryRegion containing the devices provided
* by the board model. * by the board model.
* + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
* (In hardware, the SSE-200 permits the number of expansion interrupts * (In hardware, the SSE-200 permits the number of expansion interrupts
* for the two CPUs to be configured separately, but we restrict it to * for the two CPUs to be configured separately, but we restrict it to
@ -218,7 +217,6 @@ struct ARMSSE {
/* Properties */ /* Properties */
MemoryRegion *board_memory; MemoryRegion *board_memory;
uint32_t exp_numirq; uint32_t exp_numirq;
uint32_t mainclk_frq;
uint32_t sram_addr_width; uint32_t sram_addr_width;
uint32_t init_svtor; uint32_t init_svtor;
bool cpu_fpu[SSE_MAX_CPUS]; bool cpu_fpu[SSE_MAX_CPUS];

2
include/hw/timer/cmsdk-apb-dualtimer.h
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@ -16,7 +16,6 @@
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
* *
* QEMU interface: * QEMU interface:
* + QOM property "pclk-frq": frequency at which the timer is clocked
* + Clock input "TIMCLK": clock (for both timers) * + Clock input "TIMCLK": clock (for both timers)
* + sysbus MMIO region 0: the register bank * + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: combined timer interrupt TIMINTC * + sysbus IRQ 0: combined timer interrupt TIMINTC
@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer {
/*< public >*/ /*< public >*/
MemoryRegion iomem; MemoryRegion iomem;
qemu_irq timerintc; qemu_irq timerintc;
uint32_t pclk_frq;
Clock *timclk; Clock *timclk;
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];

2
include/hw/timer/cmsdk-apb-timer.h
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@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
/* /*
* QEMU interface: * QEMU interface:
* + QOM property "pclk-frq": frequency at which the timer is clocked
* + Clock input "pclk": clock for the timer * + Clock input "pclk": clock for the timer
* + sysbus MMIO region 0: the register bank * + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: timer interrupt TIMERINT * + sysbus IRQ 0: timer interrupt TIMERINT
@ -35,7 +34,6 @@ struct CMSDKAPBTimer {
/*< public >*/ /*< public >*/
MemoryRegion iomem; MemoryRegion iomem;
qemu_irq timerint; qemu_irq timerint;
uint32_t pclk_frq;
struct ptimer_state *timer; struct ptimer_state *timer;
Clock *pclk; Clock *pclk;

2
include/hw/watchdog/cmsdk-apb-watchdog.h
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@ -16,7 +16,6 @@
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
* *
* QEMU interface: * QEMU interface:
* + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
* + Clock input "WDOGCLK": clock for the watchdog's timer * + Clock input "WDOGCLK": clock for the watchdog's timer
* + sysbus MMIO region 0: the register bank * + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: watchdog interrupt * + sysbus IRQ 0: watchdog interrupt
@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog {
/*< public >*/ /*< public >*/
MemoryRegion iomem; MemoryRegion iomem;
qemu_irq wdogint; qemu_irq wdogint;
uint32_t wdogclk_frq;
bool is_luminary; bool is_luminary;
struct ptimer_state *timer; struct ptimer_state *timer;
Clock *wdogclk; Clock *wdogclk;