MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers
are implemented. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2589 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -1375,7 +1375,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile,
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"undefined branch in delay slot at pc 0x%08x\n", ctx->pc);
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"undefined branch in delay slot at PC " TARGET_FMT_lx "\n",
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ctx->pc);
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}
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MIPS_INVAL("branch/jump in bdelay slot");
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generate_exception(ctx, EXCP_RI);
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@ -4841,9 +4842,15 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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}
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GEN_STORE_TN_REG(rt, T0);
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break;
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/* Shadow registers (not implemented). */
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case OPC_RDPGPR:
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case OPC_WRPGPR:
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if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) {
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/* Shadow registers not implemented. */
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GEN_LOAD_REG_TN(T0, rt);
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GEN_STORE_TN_REG(rd, T0);
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} else
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generate_exception(ctx, EXCP_RI);
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break;
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default:
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generate_exception(ctx, EXCP_RI);
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break;
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