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target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed

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Add a flag to MIPSCPUClass in order to avoid needing to
replace mips_tcg_ops.do_transaction_failed.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-02-27 12:44:00 -08:00
parent 6bc0d6a047
commit 3803b6b427
3 changed files with 8 additions and 33 deletions
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35
hw/mips/jazz.c
View File

@ -119,30 +119,6 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE \ #define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response,
uintptr_t retaddr);
static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response,
uintptr_t retaddr)
{
if (access_type != MMU_INST_FETCH) {
/* ignore invalid access (ie do not raise exception) */
return;
}
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
mmu_idx, attrs, response, retaddr);
}
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void mips_jazz_init(MachineState *machine, static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model) enum jazz_model_e jazz_model)
{ {
@ -151,7 +127,7 @@ static void mips_jazz_init(MachineState *machine,
int bios_size, n; int bios_size, n;
Clock *cpuclk; Clock *cpuclk;
MIPSCPU *cpu; MIPSCPU *cpu;
CPUClass *cc; MIPSCPUClass *mcc;
CPUMIPSState *env; CPUMIPSState *env;
qemu_irq *i8259; qemu_irq *i8259;
rc4030_dma *dmas; rc4030_dma *dmas;
@ -198,8 +174,6 @@ static void mips_jazz_init(MachineState *machine,
* However, we can't simply add a global memory region to catch * However, we can't simply add a global memory region to catch
* everything, as this would make all accesses including instruction * everything, as this would make all accesses including instruction
* accesses be ignored and not raise exceptions. * accesses be ignored and not raise exceptions.
* So instead we hijack the do_transaction_failed method on the CPU, and
* do not raise exceptions for data access.
* *
* NOTE: this behaviour of raising exceptions for bad instruction * NOTE: this behaviour of raising exceptions for bad instruction
* fetches but not bad data accesses was added in commit 54e755588cf1e9 * fetches but not bad data accesses was added in commit 54e755588cf1e9
@ -209,11 +183,8 @@ static void mips_jazz_init(MachineState *machine,
* we could replace this hijacking of CPU methods with a simple global * we could replace this hijacking of CPU methods with a simple global
* memory region that catches all memory accesses, as we do on Malta. * memory region that catches all memory accesses, as we do on Malta.
*/ */
cc = CPU_GET_CLASS(cpu); mcc = MIPS_CPU_GET_CLASS(cpu);
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mcc->no_data_aborts = true;
real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */ /* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram); memory_region_add_subregion(address_space, 0, machine->ram);

3
target/mips/cpu-qom.h
View File

@ -47,6 +47,9 @@ struct MIPSCPUClass {
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; DeviceReset parent_reset;
const struct mips_def_t *cpu_def; const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
bool no_data_aborts;
}; };

3
target/mips/tcg/op_helper.c
View File

@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr) MemTxResult response, uintptr_t retaddr)
{ {
MIPSCPU *cpu = MIPS_CPU(cs); MIPSCPU *cpu = MIPS_CPU(cs);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env; CPUMIPSState *env = &cpu->env;
if (access_type == MMU_INST_FETCH) { if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr); do_raise_exception(env, EXCP_IBE, retaddr);
} else { } else if (!mcc->no_data_aborts) {
do_raise_exception(env, EXCP_DBE, retaddr); do_raise_exception(env, EXCP_DBE, retaddr);
} }
} }