target/arm: Convert Cryptographic 3-register, imm2 to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -644,3 +644,13 @@ SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0
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EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3
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BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3
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SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3
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### Cryptographic three-register, imm2
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&crypto3i rd rn rm imm
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@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i
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SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i
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SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i
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SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i
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SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i
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@ -4676,6 +4676,18 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a)
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return true;
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}
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static bool do_crypto3i(DisasContext *s, arg_crypto3i *a, gen_helper_gvec_3 *fn)
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{
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if (fp_access_check(s)) {
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gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->imm, fn);
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}
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return true;
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}
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TRANS_FEAT(SM3TT1A, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt1a)
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TRANS_FEAT(SM3TT1B, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt1b)
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TRANS_FEAT(SM3TT2A, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt2a)
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TRANS_FEAT(SM3TT2B, aa64_sm3, do_crypto3i, a, gen_helper_crypto_sm3tt2b)
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/* Shift a TCGv src by TCGv shift_amount, put result in dst.
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* Note that it is the caller's responsibility to ensure that the
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* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
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@ -13604,36 +13616,6 @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)
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vec_full_reg_size(s));
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}
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/* Crypto three-reg imm2
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* 31 21 20 16 15 14 13 12 11 10 9 5 4 0
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* +-----------------------+------+-----+------+--------+------+------+
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* | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
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* +-----------------------+------+-----+------+--------+------+------+
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*/
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static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
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{
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static gen_helper_gvec_3 * const fns[4] = {
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gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b,
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gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b,
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};
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int opcode = extract32(insn, 10, 2);
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int imm2 = extract32(insn, 12, 2);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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if (!dc_isar_feature(aa64_sm3, s)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]);
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}
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/* C3.6 Data processing - SIMD, inc Crypto
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*
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* As the decode gets a little complex we are using a table based
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@ -13663,7 +13645,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
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{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
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{ 0xce800000, 0xffe00000, disas_crypto_xar },
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{ 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
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{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
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{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
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{ 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
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