target/microblaze: Convert to translator_loop
Finish the conversion to the generic translator_loop. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
d4705ae084
commit
372122e3e7
@ -1595,172 +1595,181 @@ static inline void decode(DisasContext *dc, uint32_t ir)
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}
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}
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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{
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CPUMBState *env = cs->env_ptr;
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MicroBlazeCPU *cpu = env_archcpu(env);
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uint32_t pc_start;
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struct DisasContext ctx;
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struct DisasContext *dc = &ctx;
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uint32_t page_start, org_flags;
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uint32_t npc;
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int num_insns;
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DisasContext *dc = container_of(dcb, DisasContext, base);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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int bound;
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pc_start = tb->pc;
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dc->cpu = cpu;
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org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
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dc->jmp = 0;
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dc->synced_flags = dc->tb_flags = dc->base.tb->flags;
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dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
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if (dc->delayed_branch) {
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dc->jmp = JMP_INDIRECT;
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}
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dc->base.pc_first = pc_start;
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dc->base.pc_next = pc_start;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.tb = tb;
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if (pc_start & 3) {
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cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
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}
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bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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}
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page_start = pc_start & TARGET_PAGE_MASK;
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num_insns = 0;
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static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs)
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{
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}
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gen_tb_start(tb);
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do
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{
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tcg_gen_insn_start(dc->base.pc_next);
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num_insns++;
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static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
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{
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tcg_gen_insn_start(dcb->pc_next);
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}
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static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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/*
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* The address covered by the breakpoint must be included in
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* [tb->pc, tb->pc + tb->size) in order to for it to be
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* properly cleared -- thus we increment the PC here so that
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* the logic setting tb->size below does the right thing.
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*/
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dc->base.pc_next += 4;
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break;
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}
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return true;
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}
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/* Pretty disas. */
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LOG_DIS("%8.8x:\t", (uint32_t)dc->base.pc_next);
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static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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CPUMBState *env = cs->env_ptr;
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if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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/* TODO: This should raise an exception, not terminate qemu. */
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if (dc->base.pc_next & 3) {
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cpu_abort(cs, "Microblaze: unaligned PC=%x\n",
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(uint32_t)dc->base.pc_next);
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}
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dc->clear_imm = 1;
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decode(dc, cpu_ldl_code(env, dc->base.pc_next));
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if (dc->clear_imm)
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if (dc->clear_imm) {
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dc->tb_flags &= ~IMM_FLAG;
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}
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dc->base.pc_next += 4;
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if (dc->delayed_branch) {
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dc->delayed_branch--;
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if (!dc->delayed_branch) {
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if (dc->tb_flags & DRTI_FLAG)
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if (dc->delayed_branch && --dc->delayed_branch == 0) {
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if (dc->tb_flags & DRTI_FLAG) {
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do_rti(dc);
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if (dc->tb_flags & DRTB_FLAG)
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}
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if (dc->tb_flags & DRTB_FLAG) {
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do_rtb(dc);
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if (dc->tb_flags & DRTE_FLAG)
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}
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if (dc->tb_flags & DRTE_FLAG) {
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do_rte(dc);
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}
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/* Clear the delay slot flag. */
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dc->tb_flags &= ~D_FLAG;
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/* If it is a direct jump, try direct chaining. */
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if (dc->jmp == JMP_INDIRECT) {
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dc->base.is_jmp = DISAS_JUMP;
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}
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/* Force an exit if the per-tb cpu state has changed. */
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if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
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}
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}
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static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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assert(!dc->abort_at_next_insn);
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if (dc->base.is_jmp == DISAS_NORETURN) {
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/* We have already exited the TB. */
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return;
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}
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t_sync_flags(dc);
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if (dc->tb_flags & D_FLAG) {
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sync_jmpstate(dc);
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dc->jmp = JMP_NOJMP;
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}
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switch (dc->base.is_jmp) {
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case DISAS_TOO_MANY:
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assert(dc->jmp == JMP_NOJMP);
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gen_goto_tb(dc, 0, dc->base.pc_next);
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return;
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case DISAS_UPDATE:
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assert(dc->jmp == JMP_NOJMP);
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if (unlikely(cs->singlestep_enabled)) {
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gen_raise_exception(dc, EXCP_DEBUG);
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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return;
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case DISAS_JUMP:
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switch (dc->jmp) {
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case JMP_INDIRECT:
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{
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TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next);
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eval_cond_jmp(dc, cpu_btarget, tmp_pc);
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tcg_temp_free_i32(tmp_pc);
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dc->base.is_jmp = DISAS_JUMP;
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} else if (dc->jmp == JMP_DIRECT) {
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t_sync_flags(dc);
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gen_goto_tb(dc, 0, dc->jmp_pc);
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} else if (dc->jmp == JMP_DIRECT_CC) {
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if (unlikely(cs->singlestep_enabled)) {
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gen_raise_exception(dc, EXCP_DEBUG);
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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return;
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case JMP_DIRECT_CC:
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{
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TCGLabel *l1 = gen_new_label();
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t_sync_flags(dc);
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/* Conditional jmp. */
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tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1);
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gen_goto_tb(dc, 1, dc->base.pc_next);
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gen_set_label(l1);
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}
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/* fall through */
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case JMP_DIRECT:
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gen_goto_tb(dc, 0, dc->jmp_pc);
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return;
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}
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break;
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}
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}
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if (dc->base.singlestep_enabled) {
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break;
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}
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} while (!dc->base.is_jmp && !dc->cpustate_changed
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&& !tcg_op_buf_full()
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&& !singlestep
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&& (dc->base.pc_next - page_start < TARGET_PAGE_SIZE)
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&& num_insns < max_insns);
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/* fall through */
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npc = dc->base.pc_next;
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if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
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if (dc->tb_flags & D_FLAG) {
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, npc);
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sync_jmpstate(dc);
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} else
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npc = dc->jmp_pc;
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}
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/* Force an update if the per-tb cpu state has changed. */
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
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dc->base.is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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t_sync_flags(dc);
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if (dc->base.is_jmp == DISAS_NORETURN) {
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/* nothing more to generate */
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} else if (unlikely(cs->singlestep_enabled)) {
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TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
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if (dc->base.is_jmp != DISAS_JUMP) {
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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} else {
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switch (dc->base.is_jmp) {
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case DISAS_NEXT:
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gen_goto_tb(dc, 1, npc);
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break;
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case DISAS_JUMP:
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case DISAS_UPDATE:
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/* indicate that the hash table must be used
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to find the next TB */
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tcg_gen_exit_tb(NULL, 0);
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break;
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default:
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g_assert_not_reached();
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}
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}
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gen_tb_end(tb, num_insns);
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tb->size = dc->base.pc_next - pc_start;
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tb->icount = num_insns;
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}
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static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs)
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{
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#ifdef DEBUG_DISAS
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#if !SIM_COMPAT
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(pc_start)) {
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FILE *logfile = qemu_log_lock();
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qemu_log("--------------\n");
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log_target_disas(cs, pc_start, dc->base.pc_next - pc_start);
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qemu_log_unlock(logfile);
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}
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qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first));
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log_target_disas(cs, dcb->pc_first, dcb->tb->size);
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#endif
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#endif
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assert(!dc->abort_at_next_insn);
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}
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static const TranslatorOps mb_tr_ops = {
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.init_disas_context = mb_tr_init_disas_context,
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.tb_start = mb_tr_tb_start,
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.insn_start = mb_tr_insn_start,
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.breakpoint_check = mb_tr_breakpoint_check,
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.translate_insn = mb_tr_translate_insn,
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.tb_stop = mb_tr_tb_stop,
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.disas_log = mb_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc;
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translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns);
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}
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void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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