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target-tricore: Fix new typos

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adress -> address
managment -> management

Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Stefan Weil 2015-01-03 14:41:37 +01:00 committed by Michael Tokarev
parent 90d6a6730b
commit 37097418be
3 changed files with 4 additions and 4 deletions
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2
target-tricore/csfr.def
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@ -90,7 +90,7 @@ A(0xE200, CPM0, TRICORE_FEATURE_13)
A(0xE280, CPM1, TRICORE_FEATURE_13) A(0xE280, CPM1, TRICORE_FEATURE_13)
A(0xE300, CPM2, TRICORE_FEATURE_13) A(0xE300, CPM2, TRICORE_FEATURE_13)
A(0xE380, CPM3, TRICORE_FEATURE_13) A(0xE380, CPM3, TRICORE_FEATURE_13)
/* memory Managment Registers */ /* memory management registers */
A(0x8000, MMU_CON, TRICORE_FEATURE_13) A(0x8000, MMU_CON, TRICORE_FEATURE_13)
A(0x8004, MMU_ASI, TRICORE_FEATURE_13) A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
A(0x800C, MMU_TVA, TRICORE_FEATURE_13) A(0x800C, MMU_TVA, TRICORE_FEATURE_13)

2
target-tricore/translate.c
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@ -5022,7 +5022,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
case OPCM_32_RR_LOGICAL_SHIFT: case OPCM_32_RR_LOGICAL_SHIFT:
decode_rr_logical_shift(env, ctx); decode_rr_logical_shift(env, ctx);
break; break;
case OPCM_32_RR_ADRESS: case OPCM_32_RR_ADDRESS:
decode_rr_address(env, ctx); decode_rr_address(env, ctx);
break; break;
case OPCM_32_RR_IDIRECT: case OPCM_32_RR_IDIRECT:

4
target-tricore/tricore-opcodes.h
View File

@ -503,7 +503,7 @@ enum {
/* RR Format */ /* RR Format */
OPCM_32_RR_LOGICAL_SHIFT = 0x0f, OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
OPCM_32_RR_ACCUMULATOR = 0x0b, OPCM_32_RR_ACCUMULATOR = 0x0b,
OPCM_32_RR_ADRESS = 0x01, OPCM_32_RR_ADDRESS = 0x01,
OPCM_32_RR_DIVIDE = 0x4b, OPCM_32_RR_DIVIDE = 0x4b,
OPCM_32_RR_IDIRECT = 0x2d, OPCM_32_RR_IDIRECT = 0x2d,
/* RR1 Format */ /* RR1 Format */
@ -1082,7 +1082,7 @@ enum {
OPC2_32_RR_XOR_LT_U = 0x32, OPC2_32_RR_XOR_LT_U = 0x32,
OPC2_32_RR_XOR_NE = 0x30, OPC2_32_RR_XOR_NE = 0x30,
}; };
/* OPCM_32_RR_ADRESS */ /* OPCM_32_RR_ADDRESS */
enum { enum {
OPC2_32_RR_ADD_A = 0x01, OPC2_32_RR_ADD_A = 0x01,
OPC2_32_RR_ADDSC_A = 0x60, OPC2_32_RR_ADDSC_A = 0x60,