Reorganise Sun4m to allow other machine types
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2570 c046a42c-6fe2-441c-8c8c-71466251a162
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blueswir1
parent
8a08f9a809
commit
36cd921035
193
hw/sun4m.c
193
hw/sun4m.c
@ -23,43 +23,44 @@
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*/
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#include "vl.h"
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#define KERNEL_LOAD_ADDR 0x00004000
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#define CMDLINE_ADDR 0x007ff000
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#define INITRD_LOAD_ADDR 0x00800000
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#define PROM_SIZE_MAX (256 * 1024)
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#define PROM_ADDR 0xffd00000
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#define PROM_FILENAME "openbios-sparc32"
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#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
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#define PHYS_JJ_IDPROM_OFF 0x1FD8
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#define PHYS_JJ_EEPROM_SIZE 0x2000
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// IRQs are not PIL ones, but master interrupt controller register
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// bits
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#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
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#define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
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#define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
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#define PHYS_JJ_DMA 0x78400000 /* DMA controller */
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#define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
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#define PHYS_JJ_ESP_IRQ 18
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#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
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#define PHYS_JJ_LE_IRQ 16
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#define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
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#define PHYS_JJ_CLOCK_IRQ 7
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#define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
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#define PHYS_JJ_CLOCK1_IRQ 19
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#define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
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#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
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#define PHYS_JJ_MS_KBD_IRQ 14
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#define PHYS_JJ_SER 0x71100000 /* Serial */
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#define PHYS_JJ_SER_IRQ 15
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#define PHYS_JJ_FDC 0x71400000 /* Floppy */
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#define PHYS_JJ_FLOPPY_IRQ 22
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#define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
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#define PHYS_JJ_CS 0x6c000000 /* Crystal CS4231 */
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#define PHYS_JJ_CS_IRQ 5
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#define MAX_CPUS 16
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struct hwdef {
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target_ulong iommu_base, slavio_base;
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target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
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target_ulong fd_base;
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target_ulong dma_base, esp_base, le_base;
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target_ulong tcx_base, cs_base;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller register
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// bit numbers
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int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
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int machine_id; // For NVRAM
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};
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/* TSC handling */
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uint64_t cpu_get_tsc()
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@ -122,7 +123,8 @@ extern int nographic;
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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int boot_device, uint32_t RAM_size,
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uint32_t kernel_size,
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int width, int height, int depth)
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int width, int height, int depth,
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int machine_id)
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{
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unsigned char tmp = 0;
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int i, j;
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@ -151,7 +153,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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// Sun4m specific use
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i = 0x1fd8;
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m48t59_write(nvram, i++, 0x01);
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m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
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m48t59_write(nvram, i++, machine_id);
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j = 0;
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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@ -207,25 +209,16 @@ static void main_cpu_reset(void *opaque)
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cpu_reset(env);
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}
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/* Sun4m hardware initialisation */
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static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
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DisplayState *ds, const char *cpu_model)
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{
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CPUState *env, *envs[MAX_CPUS];
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char buf[1024];
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int ret, linux_boot;
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unsigned int i;
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long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
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void *iommu, *dma, *main_esp, *main_lance = NULL;
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const sparc_def_t *def;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (cpu_model == NULL)
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cpu_model = "Fujitsu MB86904";
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sparc_find_by_name(cpu_model, &def);
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if (def == NULL) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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@ -243,34 +236,40 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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iommu = iommu_init(PHYS_JJ_IOMMU);
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slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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iommu = iommu_init(hwdef->iommu_base);
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slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
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hwdef->intctl_base + 0x10000);
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for(i = 0; i < smp_cpus; i++) {
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slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
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}
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dma = sparc32_dma_init(PHYS_JJ_DMA, PHYS_JJ_ESP_IRQ, PHYS_JJ_LE_IRQ, iommu, slavio_intctl);
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dma = sparc32_dma_init(hwdef->dma_base, hwdef->esp_irq,
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hwdef->le_irq, iommu, slavio_intctl);
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tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
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hwdef->vram_size, graphic_width, graphic_height);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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main_lance = lance_init(&nd_table[0], PHYS_JJ_LE, dma);
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main_lance = lance_init(&nd_table[0], hwdef->le_base, dma);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
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nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8);
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
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slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
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hwdef->clock_irq, 0, i);
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}
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slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
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slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
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slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
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(unsigned int)-1);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
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fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
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main_esp = esp_init(bs_table, PHYS_JJ_ESP, dma);
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slavio_serial_init(hwdef->serial_base, hwdef->ser_irq,
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serial_hds[1], serial_hds[0]);
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fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table);
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main_esp = esp_init(bs_table, hwdef->esp_base, dma);
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for (i = 0; i < MAX_DISKS; i++) {
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if (bs_table[i]) {
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@ -278,9 +277,23 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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}
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}
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slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
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cs_init(PHYS_JJ_CS, PHYS_JJ_CS_IRQ, slavio_intctl);
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slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq);
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cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
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sparc32_dma_set_reset_data(dma, main_esp, main_lance);
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}
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static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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int machine_id)
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{
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int ret, linux_boot;
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char buf[1024];
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unsigned int i;
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long prom_offset, initrd_size, kernel_size;
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linux_boot = (kernel_filename != NULL);
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prom_offset = ram_size + vram_size;
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cpu_register_physical_memory(PROM_ADDR,
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@ -329,11 +342,69 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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}
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}
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}
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, ram_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, machine_id);
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}
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QEMUMachine sun4m_machine = {
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"sun4m",
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"Sun4m platform",
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sun4m_init,
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static const struct hwdef hwdefs[] = {
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/* SS-5 */
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{
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.cs_base = 0x6c000000,
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.slavio_base = 0x71000000,
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.ms_kb_base = 0x71000000,
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.serial_base = 0x71100000,
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.nvram_base = 0x71200000,
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.fd_base = 0x71400000,
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.counter_base = 0x71d00000,
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.intctl_base = 0x71e00000,
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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.le_irq = 16,
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.clock_irq = 7,
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.clock1_irq = 19,
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.ms_kb_irq = 14,
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.ser_irq = 15,
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.fd_irq = 22,
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.me_irq = 30,
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.cs_irq = 5,
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.machine_id = 0x80,
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},
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};
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static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model,
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unsigned int machine)
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{
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sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
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sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
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kernel_filename, kernel_cmdline, initrd_filename,
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hwdefs[machine].machine_id);
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}
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/* SPARCstation 5 hardware initialisation */
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static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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if (cpu_model == NULL)
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cpu_model = "Fujitsu MB86904";
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sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model,
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0);
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}
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QEMUMachine ss5_machine = {
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"SS-5",
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"Sun4m platform, SPARCstation 5",
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ss5_init,
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};
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2
vl.c
2
vl.c
@ -6690,7 +6690,7 @@ void register_machines(void)
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#ifdef TARGET_SPARC64
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qemu_register_machine(&sun4u_machine);
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#else
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qemu_register_machine(&sun4m_machine);
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qemu_register_machine(&ss5_machine);
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#endif
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#elif defined(TARGET_ARM)
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qemu_register_machine(&integratorcp_machine);
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4
vl.h
4
vl.h
@ -1143,7 +1143,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
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/* sun4m.c */
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extern QEMUMachine sun4m_machine;
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extern QEMUMachine ss5_machine;
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void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
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/* iommu.c */
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@ -1169,7 +1169,7 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
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unsigned long vram_offset, int vram_size, int width, int height);
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/* slavio_intctl.c */
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void *slavio_intctl_init();
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void *slavio_intctl_init(uint32_t addr, uint32_t addrg);
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void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
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void slavio_pic_info(void *opaque);
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void slavio_irq_info(void *opaque);
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