ppc: Fix support for odd MSR combinations
MacOS uses an architecturally illegal MSR combination that seems nonetheless supported by 32-bit processors, which is to have MSR[PR]=1 and one or more of MSR[DR/IR/EE]=0. This adds support for it. To work properly we need to also properly include support for PR=1,{I,D}R=0 to the MMU index used by the qemu TLB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -41,17 +41,19 @@ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
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static inline void hreg_compute_mem_idx(CPUPPCState *env)
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{
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/* This is our encoding for server processors
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/* This is our encoding for server processors. The architecture
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* specifies that there is no such thing as userspace with
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* translation off, however it appears that MacOS does it and
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* some 32-bit CPUs support it. Weird...
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*
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* 0 = Guest User space virtual mode
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* 1 = Guest Kernel space virtual mode
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* 2 = Guest Kernel space real mode
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* 3 = HV User space virtual mode
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* 4 = HV Kernel space virtual mode
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* 5 = HV Kernel space real mode
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*
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* The combination PR=1 IR&DR=0 is invalid, we will treat
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* it as IR=DR=1
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* 2 = Guest User space real mode
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* 3 = Guest Kernel space real mode
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* 4 = HV User space virtual mode
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* 5 = HV Kernel space virtual mode
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* 6 = HV User space real mode
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* 7 = HV Kernel space real mode
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*
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* For BookE, we need 8 MMU modes as follow:
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*
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@ -71,20 +73,11 @@ static inline void hreg_compute_mem_idx(CPUPPCState *env)
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env->immu_idx += msr_gs ? 4 : 0;
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env->dmmu_idx += msr_gs ? 4 : 0;
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} else {
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/* First calucalte a base value independent of HV */
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if (msr_pr != 0) {
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/* User space, ignore IR and DR */
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env->immu_idx = env->dmmu_idx = 0;
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} else {
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/* Kernel, setup a base I/D value */
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env->immu_idx = msr_ir ? 1 : 2;
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env->dmmu_idx = msr_dr ? 1 : 2;
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}
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/* Then offset it for HV */
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if (msr_hv) {
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env->immu_idx += 3;
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env->dmmu_idx += 3;
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}
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env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
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env->immu_idx += msr_ir ? 0 : 2;
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env->dmmu_idx += msr_dr ? 0 : 2;
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env->immu_idx += msr_hv ? 4 : 0;
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env->dmmu_idx += msr_hv ? 4 : 0;
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}
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}
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@ -136,8 +129,13 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
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/* Change the exception prefix on PowerPC 601 */
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env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
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}
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/* If PR=1 then EE, IR and DR must be 1 */
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if ((value >> MSR_PR) & 1) {
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/* If PR=1 then EE, IR and DR must be 1
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*
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* Note: We only enforce this on 64-bit processors. It appears that
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* 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
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* exploits it.
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*/
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if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) {
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value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
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}
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#endif
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