Code provision for new PowerPC embedded target support with:
- 1 kB page size - 64 bits GPR - 64 bits physical address space - SPE extension support. Change TARGET_PPCSPE into TARGET_PPCEMB git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -23,11 +23,13 @@
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#include "config.h"
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#include <inttypes.h>
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#if !defined(TARGET_PPCEMB)
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#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
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/* When using 64 bits temporary registers,
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* we can use 64 bits GPR with no extra cost
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*/
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#define TARGET_PPCSPE
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#define TARGET_PPCEMB
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#endif
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#endif
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#if defined (TARGET_PPC64)
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@ -35,7 +37,8 @@ typedef uint64_t ppc_gpr_t;
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#define TARGET_LONG_BITS 64
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#define TARGET_GPR_BITS 64
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#define REGX "%016" PRIx64
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#elif defined(TARGET_PPCSPE)
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#define TARGET_PAGE_BITS 12
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#elif defined(TARGET_PPCEMB)
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/* e500v2 have 36 bits physical address space */
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#define TARGET_PHYS_ADDR_BITS 64
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/* GPR are 64 bits: used by vector extension */
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@ -43,11 +46,14 @@ typedef uint64_t ppc_gpr_t;
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#define TARGET_LONG_BITS 32
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#define TARGET_GPR_BITS 64
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#define REGX "%016" PRIx64
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10
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#else
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typedef uint32_t ppc_gpr_t;
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#define TARGET_LONG_BITS 32
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#define TARGET_GPR_BITS 32
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#define REGX "%08" PRIx32
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#define TARGET_PAGE_BITS 12
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#endif
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#include "cpu-defs.h"
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@ -893,7 +899,6 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address);
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int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
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int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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/*****************************************************************************/
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@ -43,7 +43,7 @@ register unsigned long T1 asm(AREG2);
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register unsigned long T2 asm(AREG3);
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#endif
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/* We may, sometime, need 64 bits registers on 32 bits target */
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#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)
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#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)
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#define T0_64 T0
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#define T1_64 T1
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#define T2_64 T2
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@ -2479,7 +2479,7 @@ void OPPROTO op_store_booke_tsr (void)
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#endif /* !defined(CONFIG_USER_ONLY) */
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/* SPE extension */
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void OPPROTO op_splatw_T1_64 (void)
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{
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@ -3198,4 +3198,4 @@ void OPPROTO op_efdtsteq (void)
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T0 = _do_efdtsteq(T0_64, T1_64);
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RETURN();
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}
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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@ -1340,7 +1340,7 @@ void do_440_dlmzb (void)
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T0 = i;
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}
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/* SPE extension helpers */
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/* Use a table to make this quicker */
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static uint8_t hbrev[16] = {
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@ -2200,7 +2200,7 @@ DO_SPE_OP1(fsctuiz);
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DO_SPE_OP1(fsctsf);
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/* evfsctuf */
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DO_SPE_OP1(fsctuf);
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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/*****************************************************************************/
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/* Softmmu support */
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@ -183,7 +183,7 @@ void do_load_403_pb (int num);
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void do_store_403_pb (int num);
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#endif
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/* SPE extension helpers */
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void do_brinc (void);
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/* Fixed-point vector helpers */
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@ -264,7 +264,7 @@ void do_evfsctsi (void);
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void do_evfsctui (void);
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void do_evfsctsiz (void);
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void do_evfsctuiz (void);
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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/* Inlined helpers: used in micro-operation as well as helpers */
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/* Generic fixed-point helpers */
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@ -338,7 +338,7 @@ static inline int _do_cntlzd (uint64_t val)
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return cnt;
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}
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/* SPE extension */
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/* Single precision floating-point helpers */
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static inline uint32_t _do_efsabs (uint32_t val)
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@ -459,5 +459,5 @@ static inline int _do_efdtsteq (uint64_t op1, uint64_t op2)
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u2.u = op2;
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return float64_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;
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}
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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#endif
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@ -37,7 +37,7 @@ static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA)
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((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
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}
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#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
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#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
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static inline uint64_t glue(ld64r, MEMSUFFIX) (target_ulong EA)
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{
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uint64_t tmp = glue(ldq, MEMSUFFIX)(EA);
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@ -79,7 +79,7 @@ static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data)
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glue(stl, MEMSUFFIX)(EA, tmp);
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}
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#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
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#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
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static inline void glue(st64r, MEMSUFFIX) (target_ulong EA, uint64_t data)
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{
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uint64_t tmp = ((data & 0xFF00000000000000ULL) >> 56) |
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@ -895,7 +895,7 @@ void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
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RETURN();
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}
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/* SPE extension */
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#define _PPC_SPE_LD_OP(name, op) \
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void OPPROTO glue(glue(op_spe_l, name), MEMSUFFIX) (void) \
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@ -1151,6 +1151,6 @@ static inline uint64_t glue(spe_lwhsplat_le, MEMSUFFIX) (target_ulong EA)
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return ret;
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}
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PPC_SPE_LD_OP(whsplat_le, spe_lwhsplat_le);
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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#undef MEMSUFFIX
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@ -57,7 +57,7 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
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}
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#endif
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
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{
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T0_64 = regs->gpr[REG];
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@ -97,7 +97,7 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
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RETURN();
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}
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#endif
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#endif /* defined(TARGET_PPCSPE) */
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#endif /* defined(TARGET_PPCEMB) */
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#if REG <= 7
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/* Condition register moves */
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@ -161,7 +161,7 @@ typedef struct DisasContext {
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int sf_mode;
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#endif
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int fpu_enabled;
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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int spe_enabled;
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#endif
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ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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@ -4761,7 +4761,7 @@ GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
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*/
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}
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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/*** SPE extension ***/
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/* Register moves */
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@ -5740,7 +5740,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
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ctx.sf_mode = msr_sf;
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#endif
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ctx.fpu_enabled = msr_fp;
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#if defined(TARGET_PPCSPE)
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#if defined(TARGET_PPCEMB)
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ctx.spe_enabled = msr_spe;
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#endif
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ctx.singlestep_enabled = env->singlestep_enabled;
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