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include/qemu/atomic.h: Add signal_barrier 

We have some potential race conditions vs our user-exec signal
handler that will be solved with this barrier.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-07-09 10:40:00 +02:00
parent 1789d4274b
commit 359896dfa4
1 changed files with 11 additions and 0 deletions
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11
include/qemu/atomic.h
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@ -88,6 +88,13 @@
#define smp_read_barrier_depends() barrier() #define smp_read_barrier_depends() barrier()
#endif #endif
/*
* A signal barrier forces all pending local memory ops to be observed before
* a SIGSEGV is delivered to the *same* thread. In practice this is exactly
* the same as barrier(), but since we have the correct builtin, use it.
*/
#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
/* Sanity check that the size of an atomic operation isn't "overly large". /* Sanity check that the size of an atomic operation isn't "overly large".
* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
* want to use them because we ought not need them, and this lets us do a * want to use them because we ought not need them, and this lets us do a
@ -308,6 +315,10 @@
#define smp_read_barrier_depends() barrier() #define smp_read_barrier_depends() barrier()
#endif #endif
#ifndef signal_barrier
#define signal_barrier() barrier()
#endif
/* These will only be atomic if the processor does the fetch or store /* These will only be atomic if the processor does the fetch or store
* in a single issue memory operation * in a single issue memory operation
*/ */